Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

Abstract: A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Abstract: Semiconductor structure and method of forming a semiconductor structure are provided. A substrate is provided, including a first region and a second region that are adjacent to each other and arranged in a first direction. Fins are disposed on a surface of the substrate at the first region, and first openings are located between adjacent fins. The fins include fins to-be-removed. A first dielectric layer is formed on sidewalls of the fins. The first dielectric layer fills the first openings. A first groove is formed in the substrate at the second region by etching the substrate at the second region using the first dielectric layer as a mask. After forming the first groove, a second groove is formed in the substrate at the first region by removing the fins to-be-removed and a portion of the substrate located at bottoms of the fins to-be-removed.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having an opening and forming a first gate layer in the opening. The first gate layer closes a top of the opening and includes a void. The method also includes forming a second gate layer on the first gate layer. An atomic radius of a material of the second gate layer is smaller than gaps among the atoms of the material of the first gate layer. Further, the method includes performing a thermal annealing process to cause atoms of the material of the second layer to pass through the first gate layer to fill the void.

Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate, and the substrate includes isolation structures; forming a first gate structure on the substrate; forming a first opening and a second opening at two sides of the first gate structure respectively, where the first opening is disposed between the first gate structure and the isolation structures, and at least a portion of sidewalls of the first opening exposes sidewalls of the isolation structure; performing a surface treatment on surface of inner walls of the first opening; and forming epitaxial layers in the first opening and in the second opening respectively, after the surface treatment.

Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins.

Abstract: Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.

Abstract: The present disclosure provides a fuse storage cell. The fuse storage cell includes a transistor and N fuse elements. The transistor includes a source, a drain, and a gate. Each fuse element of the N fuse elements includes a first terminal and a second terminal. The first terminal of the fuse element is electrically connected to the drain of the transistor, and the second terminal of the fuse is configured for inputting a read voltage or a programming voltage. N is a positive integer.

Abstract: A method of forming a method of forming a semiconductor device includes providing a semiconductor structure, etching back each gate structure of a plurality of gate structures to form an opening, forming a barrier layer over the dielectric layer, forming a sacrificial layer over the barrier layer, planarizing the sacrificial layer till a surface of the sacrificial layer is substantially flat, and using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer, and to remove the sacrificial layer and to provide a planarized barrier layer. The semiconductor structure includes a semiconductor substrate, a fin, the plurality of gate structures, and a dielectric layer over the semiconductor substrate between adjacent gate structures. A top of the dielectric layer is coplanar with a top of each of the plurality of gate structures.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; and a functional layer, on the substrate. The substrate includes a device region. The semiconductor structure further includes a plurality of discrete sidewall spacers, on the functional layer in the device region. Adjacent sidewall spacers are spaced apart by a first gap and a second gap, and the first gap and the second gap are alternately arranged. The semiconductor structure further includes: a core layer on a sidewall surface of one side of the sidewall spacer; a second opening in the functional layer at a bottom of the second gap exposed by the sidewall spacer and the core layer; and a first opening in the functional layer at a bottom of the first gap. The core layer is disposed in the second gap.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.

Abstract: Fabrication method of a semiconductor device is provided. The method includes forming an etch layer on the substrate, forming a first transitional layer and a first barrier layer on the etch layer, forming first islands on the first transitional layer by patterning the first barrier layer, forming first trenches in the first transitional layer to expose the etch layer, transferring the pattern of the first trenches into the etch layer and removing the first island, forming a second transitional layer and a second barrier layer on the etch layer and the first trenches, forming second islands on the second transitional layer by patterning the second barrier layer, forming second trenches in the second transitional layer to expose the etch layer, and transferring the pattern of the second trenches into the etch layer.

Abstract: An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

Abstract: A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove.

Abstract: A semiconductor device and its fabrication method are provided. The method includes providing a base substrate; forming a first well region and a second well region in the base substrate; forming a gate electrode structure, sidewall spacers, a doped source layer, a doped drain layer and a dielectric layer over the base substrate, where the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers, and the gate electrode structure and the sidewall spacers are over the first well region and the second well region; removing a portion of the gate electrode structure on the second well region and a portion of the base substrate of the second well region to form a trench in the dielectric layer, where the trench exposes a portion of the sidewall spacers; and forming an isolation layer in the trench.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. One form of a forming method includes: providing a base; forming a plurality of discrete mandrel layers on the base, where an extending direction of the mandrel layers is a first direction, and a direction perpendicular to the first direction is a second direction; forming a plurality of spacer layers covering side walls of the mandrel layers; forming a pattern transfer layer on the base, where the pattern transfer layer covers side walls of the spacer layers; forming a first trench in the pattern transfer layer between adjacent spacer layers in the second direction; removing a mandrel layer to form a second trench after the first trench is formed; and etching the base along the first trench and the second trench to form a target pattern by using the pattern transfer layer and the spacer layer as a mask. In the present disclosure, the accuracy of the pattern transfer is improved.

Abstract: An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided.