Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base; forming a dielectric layer on the base; forming a conductive via running through the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, wherein the protective layer covers the conductive plug; forming an aligner trench in the protective layer and the dielectric layer, wherein the aligner trench is isolated from the conductive plug; after forming the aligner trench, removing the protective layer to expose a top portion of the conductive plug; and after removing the protective layer, forming a magnetic tunnel junction (MTJ) laminated structure on the conductive plug.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing an initial base substrate having a middle region and an adjacent edge region; forming a first opening in the middle region of the initial base substrate; forming a first adjustment layer on sidewall surfaces of the first opening; and forming a plurality of second openings with a depth greater than a depth of the first opening in the edge region of the initial base substrate. A portion of the initial base substrate between the first opening and the second opening forms a first fin, a portion of the initial base substrate between adjacent second openings form a second fin. The method also includes forming an isolation structure with a top surface lower than top surfaces of the first fin and the second fins on the surface of the initial base substrate.

Abstract: Semiconductor device and fabrication method are provided. The method includes providing a substrate with a fin including a plurality of channel layers and a sacrificial layer; forming a dummy gate structure across the fin; forming first grooves in the fin on two sides of the dummy gate structure; forming a first protection layer on sidewalls of the first channel layer and the dummy gate structure; forming second grooves by etching the fin at bottoms of the first grooves; removing a portion of sidewalls of the initial second channel layer to form a second channel layer; removing the first protection layer; forming a doped source/drain layer in the first grooves and the second grooves; forming a dielectric layer over the substrate and the fin; removing the dummy gate structure and the sacrificial layers to form a gate opening; and forming a gate structure in the gate opening.

Abstract: A semiconductor structure and a formation method thereof are provided. One form of the formation method includes: providing a substrate; forming a plurality of discrete mandrel layers on the substrate, wherein a minimum pitch between mandrel layers of the plurality of mandrel layers is a second pitch, and a minimum pitch between each of other pitches is a first pitch; forming second side wall covering layer between the mandrel layers having the second pitch; removing a first side wall covering layer, and maintaining the second side wall covering layer; forming a third side wall covering layer on an exposed side wall of the mandrel layer; removing the mandrel layer and the second side wall covering layer; and etching the substrate by using the third side wall covering layer as a mask to form a desired pattern. In embodiments and implementations of the present disclosure, the mandrel layer and the second side wall covering layer are configured to define a pitch between the third side wall covering layers.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.

Abstract: Semiconductor device and transistor are provided. The semiconductor device includes a plurality of first fin structures formed on a substrate, each first fin structure having a first width along a first direction perpendicular to a length direction of the first fin structure; a plurality of second fin structures, each formed on a first fin structure and including a first region located on the first fin structure and a second region located on the first region, the first region having a second width along the first direction, and the second region having a third width along the first direction; a first isolation layer, formed on the substrate and between adjacent first fin structures and adjacent second fin structures; and a second isolation layer formed on the first region and between a bottom portion of sidewall surfaces of each second region and the first isolation layer.

Abstract: Semiconductor device and fabrication method are provided. The method includes a base substrate including a first region, a second region, and a third region arranged in a first direction; a first doped layer at the first region and a second doped layer at the third region; a first gate structure at the second region; a first dielectric layer on the base substrate; forming first trenches in the first dielectric layer, where the first trenches include second sub-regions arranged in a direction in parallel with a second direction, and a minimum distance between a second sub-region and a contact region of the first gate structure is greater than zero; forming a first conductive layer in the first trenches; forming a second conductive layer on a surface of the first conductive layer at the second sub-regions; and forming a third conductive layer on the contact region of the first gate structure.

Abstract: A semiconductor structure and fabrication method thereof are provided. The fabrication method includes: providing a base substrate including a substrate and a plurality of fins on the substrate; forming gate structures across the fins, to cover a portion of sidewalls of the fins and a portion of top surfaces of the fins; forming stress layers in the fins on sides of each gate structure; forming barrier layers on sidewalls of the gate structure; and forming doped regions by applying first ion implantation processes to the fins under the stress layers using the barrier layers as a mask.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate and forming a plurality of fins on a surface of the substrate. Along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions. The first regions are located at both sides of the second regions. The method also includes forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed. Further, the method includes forming thermal conductive layers in the first openings, and forming doped layers on top surfaces of the thermal conductive layers. A material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

Abstract: A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base, wherein a first mandrel layer and a first mask layer located on the first mandrel layer are formed on the base, and openings exposing the first mandrel layer are formed in the first mask layer; forming a second mandrel layer covering the first mask layer, wherein the second mandrel layer also fills the openings; forming first trenches running through the second mandrel layer, the first mask layer and the first mandrel layer, wherein the side walls of the first trenches expose the second mandrel layer in the openings; forming side wall layers on the side walls of the first trenches; and etching to remove the second mandrel layer and the first mandrel layer below the positions of the openings by taking the side wall layers as masks to form second trenches running through the first mandrel layer, wherein the second trenches and the first trenches are isolated by the side wall layers.

Abstract: A fabrication method for a semiconductor structure is provided. The method includes: forming a base substrate; forming gate structures on the base substrate where each gate structure includes a first gate portion with first doping ions on the base substrate and a second gate portion on the first gate portion; forming a metal layer on the second gate portions; and forming a metal silicide layer by reacting a portion of the metal layer with each second gate portion through an annealing process. When forming the metal silicide layers, a reaction between the metal layer and the second gate portions has a first reacting rate and a reaction between the metal layer and the first gate portions has a second reacting rate; and the second reacting rate is smaller than the first reacting rate.

Abstract: The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.

Abstract: A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region.

Abstract: An apparatus for detecting a defect on a surface of a substrate includes an optical microlens array disposed adjacent to the substrate and including an array of microlenses configured to direct light incident on a second surface of the optical microlens array to exit a first surface of the optical microlens array opposite the second surface for irradiating the surface of the substrate and converge light emitted from the irradiated surface of the substrate, and an imaging member including a plurality of imaging units configured to receive the converged light of the optical microlens array. Each of the imaging units corresponds to a microlens of the optical microlens array and includes a plurality of pixels and a light transmission opening for transmitting a portion of the incident light. The apparatus requires significantly less time to detect surface defects than conventional substrate surface defect detection devices.

Abstract: Semiconductor device, static random access memory (SRAM), and their fabrication methods are provided. The semiconductor device includes a base substrate with first fins formed in adjacent device regions. An isolation structure is formed on the base substrate having a top lower than the first fins. The isolation structure includes a first region and a second region, on opposite sidewalls of a corresponding first fin. The first region is between the adjacent first fins. The isolation structure has a top in the first region higher than that in the second region. A first doped layer is formed in the first fin having a portion in the second region. A dielectric layer is formed over the base substrate and a first contact hole is formed in the dielectric layer to expose a top of the first doped layer and a sidewall surface of the first doped layer, in the second region.

Abstract: A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer.

Abstract: A fin field effect transistor is provided. The FinFET device includes a base substrate; an isolation layer on the base substrate; first fins in the isolation layer and on the base substrate. The first fins is made of a material having a thermal conductivity greater than a material of the base substrate.