Abstract: An apparatus coupled to a chamber for processing extreme ultraviolet radiation includes a gas inlet configured to direct exhaust gases from the chamber into a combustion zone. The combustion zone is configured to flamelessly ignite the exhaust gases. An air inlet is configured to direct a mixture of air and a fuel into the combustion zone. A control valve is configured to change a volume of fluid exhausted from the combustion zone. A controller configured to control the control valve so as to prevent a pressure inside the combustion zone from exceeding a preset pressure value is provided.

Abstract: A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.

Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Abstract: A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a first metal connecting layer, a piezoelectric film, and an upper electrode layer; forming an acoustic resonance film by patternizing the piezoelectric film, the upper electrode layer, and the first metal connecting layer; above the base substrate, forming a second dielectric layer and a third dielectric layer; forming a first cavity through the third and second dielectric layers, and the protection layer; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer under the isolation trench layer; and forming a second cavity through the fourth dielectric layer, the isolation trench layer, and the first dielectric layer, plan views of the first and second cavities forming an overlapped region having a polygon shape without parallel sides.

Abstract: A semiconductor structure includes providing a substrate including a first surface and a second surface opposite to the first surface. The first surface is a functional surface. The method also includes forming a plastic seal layer on the first surface of the substrate, and performing a thinning-down process on the second surface of the substrate after forming the plastic seal layer. The plastic seal layer provides support for the substrate during the thinning-down process, and thus warping or cracking of the plastic seal layer 240 may be avoided. In addition, the plastic seal layer can also be used as a material for packaging the substrate. Therefore, after the thinning-down process, the plastic seal layer does not need to be removed. As such, the fabrication process is simplified, and the production cost is reduced.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.

Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.

Abstract: An apparatus for cleaning an electrostatic reticle holder used in a lithography system includes a chamber for providing a low pressure environment for the electrostatic reticle holder and an ultrasound transducer configured to apply ultrasound waves to the electrostatic reticle holder. The apparatus further includes a controller configured to control the ultrasound transducer and a gas flow controller. The gas flow controller is configured to enable pressurizing or depressurizing the chamber.

Abstract: Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

Abstract: A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.

Abstract: A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.

Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.