Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.

Abstract: Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a third die, and a second encapsulant. The first die and the second die laterally aside the first die. The first encapsulant laterally encapsulates the first die and the second die. The third die is electrically connected to the first die and the second die. The second encapsulant is over the first die, the second die and the first encapsulant, laterally encapsulating the third die. The first encapsulant includes a plurality of first fillers, the second encapsulant includes a plurality of second fillers, and a content of the second fillers in the second encapsulant is less than a content of the first fillers in the first encapsulant.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

Abstract: A high-voltage isolation semiconductor device and a method for manufacturing the same. The method includes providing a first conductivity type substrate of a substrate layer; performing first conductivity type ion implantation by means of first implantation energy to form a first conductivity type buried layer part A; performing first conductivity type ion implantation by means of second implantation energy to form a first conductivity type buried layer part B primary structure, wherein the first implantation energy is greater than the second implantation energy; growing a second conductivity type epitaxial layer on the first conductivity type substrate, wherein the first conductivity type buried layer part B primary structure extends into the second conductivity type epitaxial layer to form a first conductivity type buried layer part B; and forming a first conductivity type well region by means of first conductivity type ion implantation.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

Abstract: A method includes placing, in a layout, a plurality of first cells each having a first NFET fin number. The first cells are swapped with a plurality of second cells each having a second NFET fin number less than the first NFET fin number. After swapping the first cells with the second cells, a timing critical path in the layout is identified. Some of the second cells in the identified timing critical path are swapped with a plurality of third cells each having a third NFET fin number greater than the second NFET fin number. After swapping some of the second cells in the identified timing critical path with the third cells, an integrated circuit is fabricated based on the layout.

Abstract: A system and an operating method for automated wafer carrier handling are provided. The system includes a storage rack including a standby position and a storage position separated from each other, a first and second moving mechanism, and a controller operatively coupled to the first and second moving mechanism to control operations of the first and second moving mechanism. The storage position is for buffering a wafer carrier awaiting transfer to a load port. The first moving mechanism is movably coupled to the storage rack and provides at least one degree of freedom of movement to transfer the wafer carrier from the storage position to the standby position. The second moving mechanism is disposed over the storage rack, operatively coupled the storage rack to the load port, and provides at least one degree of freedom of movement to transfer the wafer carrier from the standby position to the load port.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A charge pump circuit includes a sub-circuit, which is a pumping stage circuit or an output stage circuit. The sub-circuit includes an input terminal, an output terminal, a transistor, a first capacitive device, a first diode device, and a second diode device. The transistor has a first source/drain (S/D) terminal coupled with the input terminal, a second S/D terminal coupled with the output terminal, and a gate terminal. The first capacitive device has a first end coupled with the gate terminal of the transistor and a second end configured to receive a first driving signal. The first diode device has a cathode coupled with the second S/D terminal of the transistor and an anode coupled with the gate terminal of the transistor. The second diode device has a cathode coupled with the gate terminal of the transistor and an anode coupled with the second S/D terminal of the transistor.

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.

Abstract: A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.

Abstract: A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.

Abstract: A semiconductor package includes a semiconductor die, a device layer, an insulator layer, a buffer layer, and connective terminals. The device layer is stacked over the semiconductor die. The device layer includes an edge coupler located at an edge of the semiconductor package and a waveguide connected to the edge coupler. The insulator layer is stacked over the device layer and includes a first dielectric material. The buffer layer is stacked over the insulator layer. The buffer layer includes a second dielectric material. The connective terminals are disposed on the buffer layer and reach the insulator layer through contact openings of the buffer layer.