Patents Assigned to Semiconductor Technologies & Instruments
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Patent number: 6173632Abstract: Apparatus for cutting single or multiple semiconductor packages from a multilayer substrate wherein the semiconductor packages are partially encapsulated by an elastomer sealant layer disposed on a polymer film layer of the substrate. The apparatus includes upper and lower die assemblies mounted for movement relative to each other on a support base. The upper die assembly includes an actuator and a die block supporting plural sets of cutter blades arranged in patterns to cut rectangular shaped semiconductor packages out of the substrate in a single cutting operation at a single station. The lower die assembly includes plural punch members movable relative to a die block, which includes a support surface for supporting the substrate in a predetermined position as determined by spaced apart locator pins on the lower die assembly registerable with corresponding locator holes in a carrier frame for the substrate.Type: GrantFiled: November 23, 1998Date of Patent: January 16, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Tan Huek Choy
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Patent number: 6151864Abstract: A system for transferring components between packing media, such as tube packing media and tape packing media, is provided. The system includes a first packing media handling system, such as a tube handling system. The system also includes a second packing media handling system, such as a tape packing media system. A component handling system can transfer components from the tubes to the taping system, or from the taping system to the tubes.Type: GrantFiled: April 28, 1999Date of Patent: November 28, 2000Assignee: Semiconductor Technologies & InstrumentsInventors: Han Chin Fong, Sua Jit Sim
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Patent number: 6128034Abstract: An inspection system determines if leads of a semiconductor device are in proper positions. Images from at least two sides of the semiconductor device are captured along with calibration marks formed in the side of a track upon which the semiconductor device is mounted. All leads and calibration marks are captured in a single video image, the images from one side of the semiconductor device being off set from the image from the other side.Type: GrantFiled: February 18, 1994Date of Patent: October 3, 2000Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Charles K. Harris, Michael C. Zemek
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Patent number: 6118540Abstract: A computer vision apparatus and methods for automatically inspecting 2-dimensional (2D) and 3-dimensional (3D) criteria of objects using a single camera and laser sources. A camera views the object under inspection which is illuminated by a first source of light to highlight the region of interest. This provides image data for 2d analysis by a computer coupled to the system. Subsequently, multiple laser sources mounted on a positioner provide the illumination for collecting images for 3 dimensional analysis. A computer with a monitor is connected to the camera to perform the inspection and analysis and for operator supervision of the system. Specific implementations provided refer to embodiments for inspecting packaged semiconductor devices such as Ball-Grid Arrays (BGAs) packages and Quad Flat Packages (QFPs) packages for package mark inspection, package defect inspection, and solder ball or lead defects.Type: GrantFiled: July 11, 1997Date of Patent: September 12, 2000Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Rajiv Roy, Michael C. Zemek, Weerakiat Wahawisan
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Patent number: 5956134Abstract: A system for transporting and inspecting, seriatim, semiconductor devices with plural prong type or solder ball type leads includes a head for transporting the semiconductor devices from one support structure, such as a tray or tube, to a second support structure, such as a tray or tape, and wherein two dimensional and three dimensional measurements of the positional accuracy of the leads is carried out during the transport process. The inspection apparatus is interposed in the transport path and includes a first optical sensor such as a CCD camera oriented to capture a two dimensional image of the semiconductor device package and compare the image with a predetermined two dimensional image store in a central processing unit (CPU).Type: GrantFiled: April 28, 1998Date of Patent: September 21, 1999Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Rajiv Roy, Michael D. Glucksman, Weerakiat Wahawisan, Paul Harris Hasten, Charles Kenneth Harris, George Charles Epp
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Patent number: 5838434Abstract: The invention is to a calibration unit (11) for use with a moveable scale reference (9) for calibration of semiconductor package outlines, the calibration unit (11) is a monolithic rectangular block which has a plurality of legs (12) formed on and integal with said rectangular block and having spacing independent from the leads on a semiconductor device.Type: GrantFiled: December 26, 1996Date of Patent: November 17, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: David A. Skramsted, Clyde M. Guest, III, Dennis M. Botkins
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Patent number: 5826630Abstract: An electronic device package lead conditioning method and system corrects bowed-in J-leads (36) of an electronic device package (30) by inserting between a bowed-in J-lead (36) and electronic device package (36) a comb-like tooth (42) having a graduating-width edge, the graduating width edge graduating from a minimum width (112) to a maximum width (114). The minimum width permits the graduating width edge (112) to be inserted into a space (110) separating the bowed-in J-lead (36) from electronic device package (30). The maximum width (114) at least equals the width of a desired spacing for the bowed-in J-lead (36) from the electronic device package (30) for correcting for the bowed-in-condition of the bowed-in J-lead (36).Type: GrantFiled: September 24, 1997Date of Patent: October 27, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Troy D. Moore, Dennis M. Botkin
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Patent number: 5777886Abstract: A lead conditioning system (10) conditions leads (74) of electronic component package (30) and includes a rotary table (16) for holding electronic component package (30) and making accessible the leads (74). A conditioning tool (20) includes conditioner arm (34) and conditioner blade (70) that selectively contacts a predetermined number of the leads (74). A manipulator (22) moves conditioning tool (20) to positions that contact a predetermined number of leads (74) to condition leads (74). A control system (24) controls the operation of manipulator (22).Type: GrantFiled: July 14, 1994Date of Patent: July 7, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Michael D. Glucksman, Weerakiat Wahawisan, Troy D. Moore, Paul H. Hasten, Dennis M. Botkin, James E. Loveless, Joseph Antao, Michael C. Zemek, Rajiv Roy
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Patent number: 5745593Abstract: Burr inspection system (120) inspects an electrical lead for a burr (112) in association with the operation of a machine vision lead inspection system (10) and includes machine vision circuitry (50) for forming an image (70) of the electrical lead (72) using machine vision lead inspection system (10). Edge detecting instructions (120) associate with machine vision circuitry (50) for determining a plurality of edges (89, 91) associated with the electrical lead (72). Scan line determining instructions (128) calculate a plurality of scan lines (88, 90) each corresponding to the contour of a selected one of the plurality of edges (89, 91). The scan lines (88, 90) are separated from edges (88, 90) and image (70) by a preselected distance (92). Inspecting circuitry (130) inspects each scan line (88, 90) to detect whether a burr image (112) crosses the scan line (88, 90) to determine the presence of a burr on the electrical lead.Type: GrantFiled: July 25, 1996Date of Patent: April 28, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Weerakiat Wahawisan, Rajiv Roy