Patents Assigned to SGS Microelettronica S.p.A.
  • Patent number: 4816702
    Abstract: A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: March 28, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Alberto Salina, Domenico Rossi, Claudio Diazzi
  • Patent number: 4816883
    Abstract: A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.
    Type: Grant
    Filed: June 22, 1987
    Date of Patent: March 28, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Livio Baldi
  • Patent number: 4817012
    Abstract: In order to identify parasitic transistors in bipolar integrated circuit structures, files relating to the parameters of the simulated circuit are established. These files are then manipulated to establish the operating parameters of the simulated circuit. These operating parameters are then examined to identify the conditions that lead to circuit degradation due to parasitic transistors. The structure in the integrated circuit that result in the parasitic transistors are then highlighted on the circuit display in order to facilitate appropriate design changes.
    Type: Grant
    Filed: April 25, 1986
    Date of Patent: March 28, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Roberta Cali'
  • Patent number: 4810902
    Abstract: An improved logic interface circuit having both a low current drain under rest conditions and a great stability in respect of temperature variations, is based on an original and effective implementation of the so-called bandgap-type voltage reference circuit, according to which the intrinsic gain of the bandgap system is not utilized, as normally happens in such voltage reference circuits for providing a negative feedback capable of compensating the temperature coefficient of the V.sub.be, but for obtaining, under open loop conditions, a transition of the output of the circuit when the input of the circuit crosses a certain threshold voltage.
    Type: Grant
    Filed: September 30, 1987
    Date of Patent: March 7, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Sandro Storti, Dominico Rossi, Giuseppe Di Natale
  • Patent number: 4808261
    Abstract: The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: February 28, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Gabriella Ghidini, Giuseppe Crisenza
  • Patent number: 4807018
    Abstract: An integrated circuit package having a semiconductor integrated circuit chip thermally and mechanically coupled to a cooling plate is described. The leadframe conductors for the package have bent end portions to bring the conductors in close proximity to the integrated circuit chip. The bent end portions of the leadframe conductors are coated with an electrically insulating material such as a varnish comprising a Teflon-based lacquer with suitable high temperature properties for permitting mechanical and thermal contact of the leadframe conductors to the heat sink or the cooling plate without electrical connection thereto. One of the leadframe conductors is adapted to engage an aperture in the cooling plate to provide a positioning mechanism and increased mechanical connection between the leadframe conductors and the cooling plate. By configuring the leadframe in an appropriate manner, conducting wires can be coupled to the chip on three sides thereof from the bent end portions of the leadframe conductors.
    Type: Grant
    Filed: October 26, 1987
    Date of Patent: February 21, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Marino Cellai
  • Patent number: 4806199
    Abstract: An improved process of RIE plasma attack of the layer of dielectric material on the surface of wafers of semiconductor material, in correspondence of areas purposely defined by masking, for exposing the underlying semiconductor crystal, in preparation for depositing a layer of material of metallic conduction. After having removed a certain thickness of dielectric according to the known technique, the conditions of attack are modified, substituting the plasma gases and reducing the "bias". The attack is resumed of the residual layer of dielectric and preferably also of a certain thickness of the semiconductor crystal in the same reactor. Ohmic contacts with relatively low contact resistance and great reliability are obtained with a minimum handling of the wafers.
    Type: Grant
    Filed: September 15, 1986
    Date of Patent: February 21, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Fabio Gualandris
  • Patent number: 4806501
    Abstract: A method is disclosed for making twin tub devices with trench isolation. The trench mask is obtained in a self-aligned manner employing tub masks that define an overlapping region at the trench. In one embodiment, the N-tub mask is defined by patterning resist (4) and polysilicon (3) overlying silicon oxide (2). The P-tub mask is defined by patterning resist (9). The oxide at the overlapping region between the tubs is removed, resulting in trench mask (2', 2") for forming trench (15). In another embodiment, the N-tub mask is defined by patterning resist (23) and silicon nitride (22). The P-tub mask is then defined by patterning resist (27) and nitride (22'). Self-aligned oxide regions (31) formed around nitride (22')serve as a trench mask for forming trench (32).
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: February 21, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Livio Baldi, Paolo G. Cappelletti
  • Patent number: 4803381
    Abstract: This circuit comprises a current source stage connectable to a capacitor which is controlled so as to alternately and periodically charge with the current fed by the source stage and discharge through a switch element, so as to generate a saw-tooth wave voltage. A buffer circuit, with low-impedance output is connected to the capacitor, for feeding a saw-tooth shaped low-impedance voltage signal to a load. In order to prevent the bias current of the buffer stage from introducing an error in the capacitor charge current and in the frequency of the saw-tooth voltage, a current sensor is provided connected between the buffer stage and the current source stage so as to vary the current generated by the source stage in an equal but opposite manner with respect to the error current due to the buffer stage.
    Type: Grant
    Filed: June 1, 1987
    Date of Patent: February 7, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Silvano Gornati, Roberto Viscardi, Silvano Coccetti
  • Patent number: 4801891
    Abstract: A voltage differential amplifier made with MOS transistors of a single channel polarity and using only two additional transistors besides a differential input pair is exceptionally exempt of problems caused by the normal spread of the parameters of the real components forming the bias current generators of the differential pair.
    Type: Grant
    Filed: October 21, 1987
    Date of Patent: January 31, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: David Novosel, Alejandro de la Plaza
  • Patent number: 4799021
    Abstract: An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the devices, besides ensuring a higher reliability. The system utilizes special "intelligent" cards, i.e. provided with a card microprocessor which may be connected to a supervisory system's CPU directing the test and classification process of the devices.
    Type: Grant
    Filed: July 15, 1987
    Date of Patent: January 17, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Lucio Cozzi
  • Patent number: 4799042
    Abstract: A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.
    Type: Grant
    Filed: December 1, 1986
    Date of Patent: January 17, 1989
    Assignee: SGS Microelettronica S.p.A
    Inventors: Pierangelo Confalonieri, Daniel Senderowicz, Germano Nicollini
  • Patent number: 4797584
    Abstract: The power-on reset circuit is adapted to automatically provide a voltage pulse as a positive supply voltage is applied.
    Type: Grant
    Filed: February 13, 1987
    Date of Patent: January 10, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Alberto Aguti, Maurizio Gaibotti, Vittorio Masina
  • Patent number: 4794349
    Abstract: A fully differential, CMOS, operational power amplifier, particularly useful as output buffer in monolithic analog subsystems, includes an input differential stage, two gain stages and two output stages. Each output stage may be individually provided with a functional feedback loop and locally compensated for reestablishing sufficient stability. An output common mode control circuit, operable in a continuous or sampled manner, is also contemplated, as well as a special circuit for controlling the DC biasing current through the output stages under rest conditions. The amplifier may be used indifferently as a balanced (differential) output or as a single-ended output amplifier without any depression of its performances.
    Type: Grant
    Filed: August 7, 1987
    Date of Patent: December 27, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Daniel Senderowicz, Germano Nicollini
  • Patent number: 4792925
    Abstract: The invention provides an EPROM memory matrix and a method of writing to an EPROM memory matrix. Two pluralities of parallel source lines alternate with parallel drain lines while floating gate areas span the source and drain lines and parallel control gate lines are arranged perpendicularly to the source and drain lines and superimposed on and self-aligned with the floating gate areas. During the writing operation, the gate and drain lines corresponding to a selected cell are connected to a positive voltage source and the source line corresponding to the selected cell is connected to earth together with all the other source lines of the same plurality while all the source lines of the other plurality are left at a potential intermediate between said positive voltage and earth.
    Type: Grant
    Filed: October 3, 1985
    Date of Patent: December 20, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Giuseppe Corda, Andrea Ravaglia
  • Patent number: 4786827
    Abstract: Described is an antisaturation circuit for an integrated PNP transistor characterized by a comparator circuit comprising two transistors and a current generator whose output current corresponds to a pre-established function, e.g., an exponential function, of the emitter current of said transistor. The changing of state of the comparator circuit, as determined by said pre-established function of said current generator, is determined by the drop of the V.sub.CE voltage of the transistor below a preset minimum value, with a portion of the conduction current of one of the two transistors of the comparator circuit utilized for increasing the forced .beta. of the transistor. This limits the degree of its saturation, as well as the leakage current toward the substrate.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: November 22, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Roberto Gariboldi, Marco Morelli
  • Patent number: 4786878
    Abstract: The low-frequency integrated amplifier comprises a voltage amplifier stage and two power amplifier stages including power amplifier means driven by the voltage amplifier stage and fedback by means of a respective feedback network dimensioned so that, at the frequency at which the phase shift of the power stages exceeds 180.degree., the open loop gain thereof is less than 0 dB, so as to prevent, for any kind of load and for every output voltage, any oscillation of said stages, and ensure the absolute stability of the system.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: November 22, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Edoardo Botti
  • Patent number: 4782288
    Abstract: This method, allowing pointing out of the effects of one manufacture parameter independently from other parameters and phenomena and yielding very high precision in measurement, comprises a first step in which a symmetrical resistive bridge is formed, comprising a pair of test resistive arms having topological characteristics related to the process or phenomenon to be evaluated and a pair of reference resistive arms. Each pair of arms is formed by two reciprocally counterposed resistors with identical topography and value. The method furthermore comprises a second step in which a current, having a known value, is applied to the bridge, the voltages present in suitable points of the bridge are measured, and the difference in conductance between the pair of test resistive arms and the reference arms is calculated according to the known or calculated current and voltage values.
    Type: Grant
    Filed: December 24, 1986
    Date of Patent: November 1, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Giuseppe Vento
  • Patent number: 4780624
    Abstract: The circuit comprises a first and a second transistor provided with the sources coupled to one end of a supply voltage and the gates coupled to one another, and a third and fourth transistor provided with the sources coupled to the other end of the supply voltage, the gates coupled to one another, the drains coupled to the respective drains of said first and second transistor, and the gates of the first and of the fourth transistor being furthermore shorted each with its own gate. The coupling between the drains of the first and of the third transistor is constituted by a preset resistor to the ends of which the base and the emitter of a bipolar transistor are coupled having the collector of the bipolar transistor coupled to one end of the supply voltage. The four transistors may be replaced by respective pairs of transistors suitably coupled to each other.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: October 25, 1988
    Assignee: SGS Microelettronica s.p.a.
    Inventors: Germano Nicollini, Daniel Senderowicz
  • Patent number: 4780430
    Abstract: The invention concerns a process for formation of a high voltage monolithic semiconductor device that contains at least one power transistor and an integrated control circuit integrated in a single chip. The device is formed by means of a triple epitaxy which utilizes the same doping agent and by growth of the third epitaxial layer with a concentration of impurities greater than the previous ones. By spreading the buried layers till they penetrate inside the third epitaxial layer, collector regions of transistors in the integrated control circuit are obtained free of unwanted intermediate layers or phantom layers caused by the outdiffusion of doping substance present in the heavily doped isolation region with conductivity of the opposite type. Finally PN junctions are formed for the collector region of a power transistor and for the isolation zone of the integrated control circuit, capable of withstanding high voltages.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: October 25, 1988
    Assignee: SGS Microelettronica S.p.A
    Inventors: Salvatore Musumeci, Raffaele Zambrano