Abstract: A method of effecting communication in a computer system between off-chip circuitry and on-chip circuitry is disclosed, according to a message protocol in which four messages can be formulated: a data write request; a data read request; a response message; and a diagnostic message.

Abstract: A system for representing a physical environment comprises a first store for holding a set of state bits, a second store for holding a set of input bits, an input device for inputting a set of initial states of said state bits into said first store, means for implementing a set of state transition functions for manipulating said input bits and said state bits, and means for generating input bits satisfying a set of constrains representing restrictions on the physical environment.

Abstract: An on-chip breakpoint unit of an integrated circuit device is connected to receive the contents of an instruction pointer register via an address communication path. The breakpoint unit has a breakpoint register configured to hold a breakpoint address at which the normal operation of the CPU is to be interrupted for diagnostic purposes, and a comparator circuit operative to compare the breakpoint address with the contents of the instruction pointer register and to issue a breakpoint signal on a breakpoint signal path when there is a match. The on-chip breakpoint unit also has circuitry configured to inhibit generation of the breakpoint signal for a next instruction to be executed upon resumption of normal operation of the CPU after it has been interrupted.

Abstract: An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Abstract: A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry.

Abstract: A computer instruction is described which expands compressed font information to provide an expanded format suitable for driving a display for example. The expansion is carried out by identifying a bit string having at least one bit sequence, selecting each bit of the bit sequence and replicating each selected bit at a plurality of adjacent locations. This is carried out in a register store having a predetermined bit capacity addressable by a single address. The instruction is particularly useful for generating background or foreground font information for driving a display.

Abstract: There is disclosed an integrated circuit comprising a test access port controller having a first mode of operation in which it is connectable to test logic to effect communication of serial test data and the control of an incoming clock signal, and a second mode of operation in which a data adaptor is connected to input and output pins via the test access port controller, the data adaptor being supplied with parallel data and control signals from on-chip functional circuitry and converting such parallel data and control signals into a sequence of serial bits including flow control bits.

Abstract: A video signal memory holds blocks of data representing luminance and first and second chrominance signals, the first and second chrominance signals being held in interleaved rows within the blocks, data being transferred from said blocks to a temporary store for use by a processor in predicting picture frames from the stored data.

Abstract: There is disclosed a single chip integrated circuit device including a message converter connected to an on-chip bus system by a first set of pins equal in number to the bit width of the bus system. The message converter has a second set of pins which are less in number than the first set. The message converter has reduced pin data receiving circuitry for receiving messages and data transmit circuitry for formulating messages from information received from the bus system. Each message has a message identifier. There is also disclosed a method of effecting memory access requests using a message converter.

Abstract: A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system. The processing system comprises a logical device for transforming the transition functions of the system into constraints on the reverse model, and a parameterization processor for applying a parameterization of the constraints to the estimate of transition functions of reverse system to form transition functions of the reverse model.

Abstract: A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.

Abstract: A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis.

Abstract: An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.

Abstract: There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

Abstract: There is disclosed a single chip integrated circuit device having a bus system, functional circuitry, and external port, and a parallel/serial data packet converter interconnecting the bus system and the external port. The parallel/serial data packet converter is operable to convert parallel data from the bus system into bit serial packets for output through the port, and allocate a packet identifier to the bit serial packets in dependence on the information received from the bus system in accordance with a predetermined protocol. A method of effecting communication between a single chip integrated circuit device and an external device using such a parallel/serial data packet converter is also disclosed.

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract: A cache memory comprises a CAM and a data RAM, the CAM has an associate input and a write input, the associate input being connected to selection circuitry to select write data or associate data so that an associate operation can be effected in parallel with a write operation using the same data to control validation of the write input.

Abstract: A method of encoding first and second symbols each having n binary bits into first and second code words each having n-1 ternary trits is disclosed. The method involves using a preselected bit from each of the first and second symbols to determine which one of at least two groups of code words comprising n-1 trits is used for encoding. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: There is disclosed a computer and a method of operating a computer to allow combination of data values in the context of the execution of so-called "packed instructions". A data string comprising a certain number of sub-strings representing discrete data values and which are not independently addressable is held in a source register store. A combining instruction which operates to carry out a polyadic operation on at least some of the sub-strings to generate a result sub-string is then executed.A result data string comprising said result sub-string is loaded into a destination register. These "combining" instructions have the advantage that they are general purpose instructions which can be used in a plurality of different situations. The instructions are particularly useful in a packed arithmetic environment.

Abstract: A method of effecting a matrix transpose operation in a computer is described. The method uses a computer instruction which restructures a data string by retaining first and last sub-strings of the data string in unchanged positions and interchanges the position of at least two intermediate sub-strings. The data string is formed from sub-strings each representing one or more data value in a matrix.The computer instruction can be effected in a single register store having a predetermined bit capacity addressable by a single address, or in a pair of such register stores.The data restructuring instructions include "flip", "zip" and "unzip" instructions.