Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.

Abstract: The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

Abstract: In transmission systems whereby data packets of a single type and having a fixed structure are used to transmit a given type of information, the invention optimizes the transmission by utilizing data packets of the same type to transmit information of different types and by differentiating the information transmitted in such packets by the rate of re-transmission thereof. In an application of the invention to RDS systems, the block PS is used to transmit both the program service name, as usual, and the radio text, and arrangements are made for the rate of re-transmission of the service name to be high and that of the text to be low, or possibly zero.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.

Abstract: The present invention relates to a system for providing a regulated voltage meant to supply a load, including a source for providing a substantially constant current approximately corresponding to the maximum current likely to be surged by the load, and a device receiving the constant current and regulating the load supply voltage, at least one capacitor being connected between an output terminal of the regulation device and the ground.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface, when the gain or the sensitivity of the lateral component is to be increased.

Abstract: A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: An integrated circuit comprising a logic processor and a fuzzy logic coprocessor is disclosed which processes a plurality of analog inputs. The logic processor and fuzzy logic processor are combined in the form of a single integrated circuit. The integrated circuit accepts a plurality of analog inputs which are digitized and provided as output to a display peripheral or are used to control an actuator peripheral such as a control unit for a valve. The integrated circuit includes means for loading or exchanging informational elements with other units of an installation.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.