Abstract: The present invention relates to an assembly ring, on a test head, of a wafer that provides an interface of electric contact transfer between the test head and a circuit to be tested, including a disk, open in its central portion and meant for supporting the periphery of the wafer; a removable collar assembly of the ring on the test head; and means for rotatably connecting the disk in the vicinity of a free end of the collar.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: Static current consumption in a low-side output drive stage is eliminated by employing a switch in series with a current generator that is employed for controlling the discharge process of the driving node (gate) of the output power transistor and by controlling the switch with the voltage that is present on the driving node of the out put power transistor.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: The present invention relates to an active analog filter including a differential amplifier, an output of which provides a filtered signal and a non-inverting input of which is connected to a median potential between supply potentials of the amplifier, a first series association of a first fixed resistor and a first variable resistor between an input terminal of a signal to be filtered and an inverting input terminal of the amplifier, a second series association of a second fixed resistor and a second variable resistor between the output of the amplifier and its inverting input terminal, and a third variable resistor in series with a filtering capacitor, between a midpoint of one of the series associations and the median potential.

Abstract: A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M1) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M2) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.

Abstract: To resolve a problem of the repairing of an electronic system, a machine will undergo a learning stage during the replacement of a part of the machine. This learning stage can be monitored manually or automatically on a limited range of variation. During this learning stage, readings are taken of the resultant modifications on a structure of the membership functions and of interference rules, memorized in a fuzzy logic program that controls the machine. These membership functions and/or theses rules are then modified as a function of this results. It is shown that it is possible, in this way, to repair a machine without replacing a defective part by a strictly identical part and without having to bring the machine back to the laboratory.

Abstract: A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input capacitor. An operational amplifier is included having a non-inverting terminal connected to a ground reference terminal, an inverting input terminal, and an output terminal feedback connected to the inverting input terminal and held in a virtual ground condition by a parallel of first and second charge paths which are connected between the input terminal of the switched input circuit structure and the inverting input terminal of the operational amplifier and connected to the supply voltage reference and the ground reference, respectively.

Abstract: The present invention relates to a control circuit of a vibrating membrane excited by a solenoid in series with a d.c. supply and a controlled switch. A capacitor is disposed across a series circuit including the solenoid and the switch associated with opening means in the vicinity of a zero crossing of the current in the inductance.

Abstract: The short-circuit detecting device includes a current generator for generating a current (IIN) of predetermined intensity, selectively into or out of the terminal (IN), and a first voltage comparator connected to the terminal (IN) and connected to the current generator in a manner such that the generator generates a current (IIN) in the inward direction and in the outward direction relative to the terminal (IN), respectively, when the voltage between the terminal (IN) and the ground is greater than a first level and less than a second level, respectively. The first level is greater than or equal to the second.

Abstract: The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base polysilicon layer and a silicon oxide layer; forming an opening in these last two layers; performing a thermal anneal in an oxidizing atmosphere; depositing a silicon nitride layer and a spacer polysilicon layer; depositing an emitter polysilicon layer; and making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node.

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming

Abstract: A method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers wherein, after a preliminary step of providing contact holes in a layer of dielectric material: a prebarrier layer of Ti or TiN is formed overall; a layer of tungsten is formed by chemical vapor deposition so as to coat the bases and the walls of the contact holes uniformly; aluminum or an alloy thereof is sputter-deposited, under high-temperature low-flux conditions, to fill the contact holes; and patterning the aluminum and tungsten layers to form metallic interconnections of predetermined geometry.

Abstract: The present invention relates to a circuit for allocating a channel to a transmission between at least two modems that use an electric network as a medium for the transmission of a binary data flow. The circuit includes, on the receive side, a device for selecting a channel that is selected for having the best transmission level according to the energy received on several transmission channels. The transmission of the binary data flow occurs, at least at the beginning of each communication on the several channels.

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: In a system of information processing by fuzzy logic, force coefficients are associated with values of variables processed by a fuzzy logic processor. The force coefficients show the degree of urgency with which information sent has to be taken into consideration or indicating the imperative nature of this information. In a network structure, this force coefficient is incorporated into address signals conveyed on the network. Then, in the membership function memories of the fuzzy logic processors, there are memories that take account of the classes of addresses for the extraction therefrom of the character of urgency of the information elements concerned.

Abstract: The fuzzy filtering of a noise signal comprising a plurality of signal samples [s(t,k)] is carried out using as variables the variation of the signal in the considered window and the distance of the samples from a sample to be reconstructed, to distinguish the typical variations of the original signal from those due to the noise and to identify the signal fronts. The method comprises the steps of defining a current signal sample [s(t)] from among the plurality of signal samples, calculating a plurality of difference samples [D(t,k)] as the difference in absolute value between the current signal sample and each signal sample and defining distance values (k) between the current signal sample and each signal sample.