Abstract: In transmission systems whereby data packets of a single type and having a fixed structure are used to transmit a given type of information, the invention optimizes the transmission by utilizing data packets of the same type to transmit information of different types and by differentiating the information transmitted in such packets by the rate of re-transmission thereof. In an application of the invention to RDS systems, the block PS is used to transmit both the program service name, as usual, and the radio text, and arrangements are made for the rate of re-transmission of the service name to be high and that of the text to be low, or possibly zero.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.

Abstract: A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique.

Abstract: A method for the formation of a region of silicon dioxide on a substrate of monocrystalline silicon. The epitaxial growth of a silicon layer, the opening of holes in the silicon layer above the silicon dioxide region, and the removal of the silicon dioxide which constitutes the region by means of chemical attack through the holes until a silicon diaphragm, attached to the substrate along the edges and separated therefrom by a space, is produced. In order to form an absolute pressure microsensor, the space has to be sealed. To do this, the method provides for the holes to have diameters smaller than the thickness of the diaphragm and to be closed by the formation of a silicon dioxide layer by vapor-phase deposition at atmospheric pressure.

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of “precursor nuclei” of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

Abstract: The method inlcudes the steps of forming a sacrificial buried region of insulating material on a substrate of monocrystalline semiconductor material, epitaxially growing a first semiconductor material layer on the substrate, the first semiconductor material layer including a polycrystalline region over the sacrificial buried region and a monocrystalline region elsewhere, the substrate and the semiconductor material layer surrounding the sacrificial buried region on all sides, and removing the sacrificial buried region. The portion of the polycrystalline region surrounded by the trench thus forms a suspended structure separated and isolated thermally from the rest of the semiconductor material layer. Using microelectronics processes, electronic components are formed in the monocrystalline region, and dedicated regions are formed at the suspended structure, so that the electronic components are integrated in the same chip with static, kinematic or dynamic microstructures.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of “precursor nuclei” of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

Abstract: The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.

Abstract: The invention relates to a method of coding and storing fuzzy logic rules, and to a circuit architecture for processing such rules. The method provides for at least one inference rule of the IF/THEN type, having a predetermined number of antecedent parts of fuzzy variables and at least one consequent part, to be dismembered and stored into memory words to allow subsequent processing using logic operators of the AND/OR/NOT type. The coding of rules and variables is effected sequentially. Thus, the occupation of memory locations can be minimized. Specifically, the rules are coded through a multi-word description, such that the number of words coding each rule is a varying number dependent on the number of antecedent parts in the rule.

Abstract: The pressure sensor is integrated in an SOI (Silicon-on-Insulator) substrate using the insulating layer as a sacrificial layer, which is partly removed by chemical etching to form the diaphragm. To fabricate the sensor, after forming the piezoresistive elements and the electronic components integrated in the same chip, trenches are formed in the upper wafer of the substrate and extending from the surface to the layer of insulating material; the layer of insulating material is chemically etched through the trenches to form an opening beneath the diaphragm; and a dielectric layer is deposited to outwardly close the trenches and the opening. Thus, the process is greatly simplified, and numerous packaging problems eliminated.

Abstract: Static current consumption in a low-side output drive stage is eliminated by employing a switch in series with a current generator that is employed for controlling the discharge process of the driving node (gate) of the output power transistor and by controlling the switch with the voltage that is present on the driving node of the out put power transistor.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.