Patents Assigned to Shanghai Hua Hong NEC Electronics
  • Patent number: 9478640
    Abstract: An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: October 25, 2016
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Wensheng Qian
  • Patent number: 9136374
    Abstract: A method of fabricating a P-type surface-channel laterally diffused metal oxide semiconductor device includes forming a gate structure with polysilicon and metal silicide, and the processes of channel implantation, long-time high-temperature drive-in, formation of a heavily doped N-type polysilicon sinker and boron doping of a polysilicon gate, are performed in this order, thereby ensuring the gate not to be doped with boron during its formation. The high-temperature drive-in process is allowed to be carried out to form a channel with a desired width, and a short channel effect which may cause penetration or electric leakage of the resulting device is prevented. As the polysilicon gate is not processed by any high-temperature drive-in process after it is doped with boron, the penetration of boron through a gate oxide layer and the diffusion of N-type impurity contained in the heavily doped polysilicon sinker into the channel or other regions are prevented.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 15, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Zhengliang Zhou, Han Yu, Biao Ma
  • Patent number: 9130003
    Abstract: A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: September 8, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS
    Inventor: Wensheng Qian
  • Patent number: 9123803
    Abstract: A semiconductor device includes: a P+ substrate; a P? epitaxial layer over the P+ substrate; a P-well and an N? drift region in the P? epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N? drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P? epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P? epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N? drift region. A method for fabricating the semiconductor device is also disclosed.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 1, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Shengan Xiao
  • Patent number: 9086545
    Abstract: An optical fiber clamp and fabrication method thereof are disclosed. The optical fiber clamp includes one or more clamp units. Each clamp unit includes a clamp body formed of silicon, a guide hole formed under a top surface of the clamp body, the guide hole having an upper diameter greater than a lower diameter of the guide hole and having an inclined sidewall; and a locating hole connected to and extends downward from a bottom of the guide hole through the clamp body, the locating hole having an upper diameter equal to a lower diameter of the locating hole and smaller than the lower diameter of the guide hole.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 21, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS
    Inventor: Lei Wang
  • Patent number: 9059277
    Abstract: A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, wherein a lightly doped n-type drain region has a laterally non-uniform n-type dopant concentration distribution, which is achieved by forming a moderately n-type doped region, having a higher doping concentration and a greater depth than the rest portion of the lightly doped n-type drain region, in a portion of the lightly n-type doped region proximate to the polysilicon gate. The structure enables the RF LDMOS device of the present invention to have both a high breakdown voltage and a significantly reduced on-resistance. A method of fabricating such a RF LDMOS device is also disclosed.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: June 16, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Juanjuan Li, Wensheng Qian, Feng Han, Pengliang Ci
  • Patent number: 9029948
    Abstract: An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and being formed in the substrate; a doped region having the first type of conductivity and being formed in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and a heavily doped drain region having the second type of conductivity and being formed in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region. A method of fabricating LDMOS device is also disclosed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 12, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Wensheng Qian
  • Patent number: 9012279
    Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 21, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8907421
    Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 9, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8895404
    Abstract: A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co. Ltd.
    Inventors: Lei Wang, Xiaobo Guo
  • Patent number: 8878370
    Abstract: A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Qing Su
  • Patent number: 8866189
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 21, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Jun Hu, Jing Shi, Wensheng Qian, Donghua Liu, Wenting Duan, Fan Chen, Tzuyin Chiu
  • Patent number: 8853771
    Abstract: A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel to a plurality of parallel arranged first trenches in a current-flowing area, while the second sides are perpendicular to the first sides and the first trenches. Such design ensures that Miller indices of sidewalls and bottom face of any portion of each second trench belong to the same family of crystal planes. Moreover, with this design, the corner portions of the second trenches can be filled with a silicon epitaxial material at the same rate with the rest portions thereof, which ensures for the second trenches to be uniformly and completely filled without any defects in the corner portions and hence improve the performance of the superjunction device.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: October 7, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Liang Yao, Jiquan Liu, Yuanyuan Yu
  • Patent number: 8829650
    Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Donghua Liu, Jun Hu, Wenting Duan, Wensheng Qian, Jing Shi
  • Patent number: 8816400
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 26, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventor: Wensheng Qian
  • Patent number: 8803280
    Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: August 12, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Qing Su
  • Patent number: 8803279
    Abstract: A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: a first polysilicon layer located below the isolation regions, and a second polysilicon layer located on and in contact with the first polysilicon layer, the first polysilicon layer being doped with a dopant having a higher diffusivity or higher concentration than a dopant of the second polysilicon layer, wherein a depth of the polysilicon stacks is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the second polysilicon layer; and the depth of the second polysilicon layer is greater than a depth of the isolation regions.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 12, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Wensheng Qian
  • Patent number: 8785977
    Abstract: A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
  • Patent number: 8779473
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Jing Shi, Wenting Duan, Wensheng Qian, Jun Hu