Abstract: The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.

Abstract: The present application discloses a method for preparing a pixel cell of a CMOS image sensor. Process optimization and adjustment for multiple times of ion implantation in a pixel area of the CMOS image sensor are carried out. That is, photodiode N-type ion implantation is performed before formation of a polysilicon gate of each MOS transistor of a CMOS pixel readout circuit, a photoresist open area is enlarged by means of a photoresist dry etching descum process such that an N-type ion implantation area is enlarged, and second photodiode N-type ion implantation is performed on the basis of the photoresist dry etching descum process, so as to achieve two times of photodiode N-type ion implantation using the same mask, with different depths and different pattern sizes, thereby forming an N-type area of the photodiode that tapers to the bottom, saving a mask layer, and reducing photolithography steps.

Abstract: This application discloses a system for turning off power consumption of an auxiliary startup circuit. An oscillator generates a switch control signal based on a reference current output by a circuit to be started up to generate a working clock of a switch control signal generation circuit after the circuit to be started up works normally. After fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control power consumption of normally open current of the auxiliary startup circuit to be turned off. At the same time, the switch control signal generation circuit stops counting the clock. This application can assist the circuit to be started up having a “degeneracy” bias point to power on normally, and can also turn off the power consumption of the auxiliary startup circuit after the circuit to be started up is powered on.

Abstract: The present application discloses a method for making an image sensor, wherein an additional supplementary oxide layer is added in a PD area of a pixel cell before the formation of a gate oxide layer, a layer of a first photoresist is added and photoetching is used to define a PD area of a non-pixel cell, a supplementary oxide layer outside the PD area is removed by etching, retaining the supplementary oxide layer in the PD area. Thus, a relatively thick oxide layer can be formed in the PD area before polysilicon generation, blanket etching can be performed on the surface of the PD area during subsequent DG-ET (double-gate etching) and poly etch, and surface damage can be avoided during etching, reducing the plasma interference, and ultimately, the pixel dark current to improve pixel performance.

Abstract: This application discloses a unit structure of a silicon photomultiplier tube, including a first conductive type heavily doped first electrode region located on a first side of the shallow trench isolation, a second conductive type heavily doped second electrode region located on a second side, and a quenching resistor located on a top surface of the shallow trench isolation. A photosensitive layer is formed in the silicon substrate at bottoms of the first electrode region, the shallow trench isolation and the second electrode region. The first electrode region, the photosensitive layer and the second electrode region form a Geiger mode avalanche photodiode. A first end of the quenching resistor is connected to the first electrode region through a first metal interconnect structure. A second end of the quenching resistor is connected to a first electrode. The second electrode region is connected to a second electrode.

Abstract: This application discloses a non-volatile memory. A device unit structure includes a vertical channel region and a gate structure. The gate structure covers one side surface of the vertical channel region. The gate structure includes a selection gate and a storage gate. The selection gate and the vertical channel region are spaced apart by a first gate dielectric layer. The selection gate and a semiconductor substrate are spaced apart by a first dielectric layer. The storage gate is located at a top of the selection gate, and the storage gate and the selection gate are spaced apart by a second dielectric layer. The storage gate and the vertical channel region are spaced apart by a second gate storage dielectric layer. A surface of the vertical channel region covered by the gate structure is used for forming a vertical channel. A second vertical channel part is controlled by the storage gate.

Abstract: The present application provides a fixing apparatus for a furnace wire of a furnace body heater, which is formed by assembling a plurality of fixing units. A structure of each of the fixing units includes: a front end structure and a tail end structure connected together. The front end structure is provided with a first recess and a second recess. The tail end structure is provided with a third recess and a fourth protrusion block. Two adjacent ones of the fixing units form a first splice structure, in the first splice structure, the fourth protrusion block of the fixing unit at the top is snap fitted in the third recess of the fixing unit at the bottom to achieve fixation. An opening of a first recess of the fixing unit at the bottom and an opening of a second recess of the fixing unit at the top are butt-jointed together.

Abstract: The present application provides an injector mounting apparatus of a furnace, wherein a first injector in the furnace has a main injector pipe. The injector mounting apparatus includes a first mounting component. The first mounting component has an injector mounting hole for the first injector to pass through and be disposed therein, a first edge on a side of the main injector pipe close to the inner side surface of the process tube abuts on a second edge on a side of the injector mounting hole close to the inner side surface of the process tube, and there is a first spacing between the second edge and an outer side face of the first mounting component. A flange is disposed at the bottom of the process tube, and the first mounting component is mounted on the flange by means of a first fixing member.

Abstract: This application discloses a method for monitoring a ghost image of a illumination unit of a lithography machine, which includes step 1: setting a lens area, a peripheral area, and a central area on a moving plane of a measurement platform; light leakage in the peripheral area causing a ghost image; step 2: turning on the illumination unit, moving the measurement platform to move the light intensity uniformity sensor to the central area, measuring first light intensity in the central area, and obtaining a reference value from the first light intensity; step 3: moving the light intensity uniformity sensor to a selected position in the peripheral area and measuring second light intensity at the selected position; and step 4: dividing the second light intensity by the reference value to obtain a first ratio as a scattered light monitoring value for the ghost image.

Abstract: This application discloses a system for turning off power consumption of an auxiliary startup circuit. An oscillator generates a switch control signal based on a reference current output by a circuit to be started up to generate a working clock of a switch control signal generation circuit after the circuit to be started up works normally. After fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control power consumption of normally open current of the auxiliary startup circuit to be turned off. At the same time, the switch control signal generation circuit stops counting the clock. This application can assist the circuit to be started up having a “degeneracy” bias point to power on normally, and can also turn off the power consumption of the auxiliary startup circuit after the circuit to be started up is powered on.

Abstract: This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

Abstract: This application discloses a method for analyzing a wafer angle in semiconductor integrated circuit manufacturing, including step 1: collecting machine angle data; step 2: predicting and forming an angle trajectory map of each analyzed wafer in a process according to the machine angle data; step 3: performing first grouping on defective wafers in an analyzed lot according to defect types; step 4: selecting one first group as a selected group, and performing second grouping on each defective wafer in the selected group according to defect directions; and step 5: calculating a direction difference between defect directions of second groups, and determining a site and a machine where a defect occurs in combination with the direction difference and an angle difference in the angle trajectory map of each detective wafer in the selected group. This application further discloses a system for analyzing a wafer angle in semiconductor integrated circuit manufacturing.

Abstract: The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.

Abstract: The present disclosure provides a CMOS image sensor and a pixel structure thereof, and a method for manufacturing a deep trench isolation grid structure in the pixel structure. The method for manufacturing the deep trench isolation grid structure comprises: depositing a first isolation layer and a second isolation layer sequentially on the side walls and bottom surface of each deep trench; and depositing a third isolation layer that fills each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute the grid. The deep trench isolation grid structure formed by the method can effectively reduce electrical crosstalk between adjacent grid lines, thereby improving the device performance of the CMOS image sensor which is built upon the deep trench isolation grid structure and the pixel structure thereof.

Abstract: The present application discloses a method for forming a mixed substrate. By optimizing the process flow, adding a silicon oxide sidewall process and covering an SOI area sidewall after dry etching with protective silicon oxide, epitaxial silicon growth on the SOI area sidewall is prevented, so that a bulge is prevented from being formed at a boundary between an SOI area and a silicon substrate area when the silicon substrate area is formed on an SOI silicon wafer. At the same time, since STI is eventually formed at the boundary between the SOI area and the silicon substrate area, the actual structure of a device formed on the mixed substrate remains basically unchanged, thus improving the product yield. The method for forming the mixed substrate is particularly suitable for an SOI gate-last process.

Abstract: The present application discloses a CMOS image sensor. A pixel cell circuit comprises a photodiode and a CMOS pixel readout circuit. The pixel cell circuit is formed on an SOI substrate, and the photodiode is formed on a bottom semiconductor substrate. The CMOS pixel readout circuit is formed on a top semiconductor substrate. A photo-induced carrier of the photodiode is connected to the CMOS pixel readout circuit by means of an electrotransfer structure passing through a dielectric buried layer. The present application also discloses a method for manufacturing a CMOS image sensor. The present application can increase a pixel cell density without reducing a photodiode area, thus achieving an ultra-high CMOS image sensor density and improving the device quality.

Abstract: The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.

Abstract: The present application discloses an optical waveguide structure, comprising: a lower cladding layer composed of a first dielectric layer; and a core layer which is composed of a patterned structure of a second material layer and presents a strip structure. A first trench is formed in a top region of the core layer. An upper cladding layer fully fills the first trench, extends to a top surface of the core layer outside the first trench, and coats side faces of the core layer in a width direction of the core layer. A refractive index of the second material layer is greater than a refractive index of the first dielectric layer, and the refractive index of the second material layer is greater than a refractive index of the upper cladding layer. The present application also provides a method for manufacturing an optical waveguide structure.

Abstract: The present application discloses a method for analyzing a layout pattern density, comprising: step 1, providing layouts of a chip, and merging the layouts to form a wafer level layout, wherein the wafer level layout presents a first circle in a top view, and the layout comprises a plurality of mask layers; step 2, segmenting the first circle to form a plurality of check windows; step 3, searching for the mask layer containing the patterns having a height morphology, and combining the found mask layers into a pattern layer combination; step 4, sequentially calculating a pattern density of the pattern layer combination in each check window; and step 5, recording the pattern density in each check window on a third circle to form a wafer level pattern density distribution diagram. The present application can predict a height morphology of a top surface of a wafer related to a layout.

Abstract: The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.