Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Abstract: The present invention includes a voltage controlled oscillator circuit and a phase-locked loop device. The voltage controlled oscillator circuit comprises: a voltage-to-current conversion module, used for converting a control voltage of a voltage controlled oscillator into a control current as a linear function of the control voltage; and a current controlled oscillation module, used for outputting a low-amplitude oscillation signal based on the control current, so as to reduce power consumption. Further provided in the present invention is a phase-locked loop device comprising the voltage controlled oscillator circuit. According to the voltage controlled oscillator circuit, design parameters of low power consumption and high linearity may be achieved, thereby making a gain Kvco of the voltage controlled oscillator relatively stable, and it may be ensured that the voltage controlled oscillator and the phase-locked loop comprising the same have relatively excellent device performance.

Abstract: The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

Abstract: The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: a P-type substrate; an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and the N-type well 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode is in mirror symmetry with a second electrode with respect to the P-type heavily doped region 24, and shallow trench isolations are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and the N-type heavily doped region 26.

Abstract: A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

Abstract: A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta2O5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.

Abstract: A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method therefor. The manufacturing method for a semiconductor device is provided for forming through-holes in a semiconductor device, comprising: forming a plurality of shallow trench isolations in portions of a substrate corresponding to memory cell regions; forming a plurality of gates on surfaces of the portions of the substrate; forming spacers on side walls at both sides of the gates extending in the first direction; depositing a sacrificial layer on the memory cell region; removing portions of the sacrificial layer corresponding to the shallow trench isolations at memory cell drain, and depositing an isolation dielectric on the shallow trench isolations at the memory cell drain to form isolation strips; and removing the remaining sacrificial layer to form bottom through-holes in spaces formed after removing the remaining sacrificial layer.

Abstract: The present disclosure relates to semiconductor devices, specifically discloses a method and an apparatus for ion implantation. The above method may comprise: generating a particle beam that satisfies the implantation energy, wherein the particle beam comprises the target ion and the impurity particle; applying a first deflection magnetic field to the particle beam to deflect the particle beam, and applying a second deflection magnetic field to the deflected particle beam to cause a second deflection of the particle beam to separate the target ion from the impurity particle; and implanting the separated target ion into the semiconductor wafer.

Abstract: Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.

Abstract: The present invention discloses a design method of a sub resolution assist feature, which comprises the following steps of: S01: forming a sub resolution assist feature in the mask plate, the upper surface of the sub resolution assist feature is aligned with the upper surface of the mask plate; S02: forming a process pattern on one side, which contains the sub resolution assist feature, of the mask plate, the position of the process pattern is not superposed with the sub resolution assist feature in a vertical direction.

Abstract: The present invention discloses a design method of a sub resolution assist feature, which comprises the following steps of: S01: forming a sub resolution assist feature in the mask plate, the upper surface of the sub resolution assist feature is aligned with the upper surface of the mask plate; S02: forming a process pattern on one side, which contains the sub resolution assist feature, of the mask plate, the position of the process pattern is not superposed with the sub resolution assist feature in a vertical direction.

Abstract: A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.

Abstract: The present invention discloses a method for quickly establishing lithography process condition by a pre-compensation value, comprising: firstly determining a reference process condition of masks of which parameters are same, and then determining an optimum process condition of the first mask; thereafter, calculating a ratio of the optimum process condition of the first mask deviating from the reference process condition, wherein if the ratio is equal to or larger than a set threshold, the first mask is inspected, and if the ratio is less than the set threshold, an optimum process condition of the second mask is determined according to the ratio and the reference process condition of the second mask; and by analogy, determining optimum process conditions of the rest masks. The method of the present invention can quickly establish a lithograph process condition, reduce the trial production time for determining the optimum defocus amount and exposure amount.

Abstract: The present invention provides a structure of a clock distribution network and generation method thereof. The clock distribution network is distributed in multiple local circuit modules. The clock distribution network comprises a clock tree structure and clock mesh structures, wherein the clock tree structure is distributed at least between or among the multiple local circuit modules and has a root node which is a clock access point of the clock distribution network. The clock mesh structures are distributed within at least one local circuit module at least according to a proportion of clock nodes in the local circuit module, a proportion of sequential circuits connected by clock in the local circuit module, a ratio of a total length of clock routing wirings in the local circuit module to a perimeter of the local circuit module, and a proportion of timing violation paths in the local circuit module.

Abstract: The present disclosure provides a manufacturing method for a transistor with an SONOS structure, including providing a semiconductor substrate, wherein the semiconductor substrate includes a select transistor well and a memory transistor well; depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well, depositing a barrier wall over adjacent portions of the select transistor well and the memory transistor well, depositing polycrystalline silicon covering the oxide layer, the ONO memory layer, and the barrier wall, and etching the polycrystalline silicon, to retain the polycrystalline silicon deposited on both sides of the barrier wall so as to form a select gate and a memory gate, and removing the oxide layer and the ONO layer on a surface of the semiconductor substrate other than the select gate, the barrier wall, and the memory gate.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure.