Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.

Abstract: A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

Abstract: The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension.

Abstract: The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a diamond-shaped cavity, and the shaped cavity is filled with silicon and germanium material. There are other embodiments as well.

Abstract: The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that this later to be filled with SiGe material. The shape cavity comprises convex regions interfacing the substrate. There are other embodiments as well.

Abstract: A method of removing a dummy gate dielectric layer is provided. Firstly a first plasma containing F is utilized to remove the dummy dielectric layer which contains Si and O. Then a second plasma containing H2 is utilized to remove fluorine compound on the surface of the semiconductor substrate. Since the fluorine residue formed after the first plasma treatment reacts with the second plasma to form a gaseous product HF, the fluorine element can be taken away from the semiconductor device with the HF, which prevents inversion layer offset and gate current leakage occurred in the subsequent processing steps due to the fluorine element.

Abstract: A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes.

Abstract: The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer, selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.

Abstract: A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.

Abstract: The present invention discloses a floating gate flash memory device, comprising: a P-type substrate which has a source and a drain, and a first polysilicon gate, a first control gate and a second polysilicon gate and a second control gate which are respectively located in parallel on the upper and lower sides of the substrate, first and second polysilicon floating gates being respectively provided between the first and second control gates and the substrate; the floating gate flash memory device of the present invention utilizes a double-gate structure, can solve the problems such as the poor programming efficiency of the floating gate flash memory and the high programming current power consumption, by using the compilation mechanism of source side injection.

Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate; defining a trench opening region of the substrate; performing plasma etching to form a trench region at the trench opening region; subjecting the substrate to a first epitaxial process with a first plurality of gaseous species to form a protective layer overlaying at least the first sidewall and the bottom of the trench region; and subjecting the substrate and the protective layer to a second epitaxial process with a second plurality of gaseous species to form a filling material overlaying the protective layer and being positioned at least partially within the trench region. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance.

Abstract: The invention provides a temperature balancing device for a projection objective of a lithography machine. The device comprises at least one temperature sensor, at least one heat-absorbing light-transmitting layer and an objective temperature balancing control unit, wherein the temperature sensor is disposed adjacent to the projection objective for sensing the temperature difference of the projection objective in different areas; the heat-absorbing light-transmitting layer is positioned below the projection objective for absorbing radiation energy in the laser beams transmitted from the lithography machine and transmitting the laser beams; and the objective temperature balancing control unit is used for controlling the absorption degree and light transmission degree of the heat-absorbing light-transmitting layer according to the temperature difference sensed by the temperature sensor. The invention also discloses a method for balancing temperature of a projection objective of a lithography machine.

Abstract: A method of depositing phosphosilicate glass (PSG) is disclosed. The method includes a first deposition step for depositing a first PSG layer with a sputtering deposition ratio of 0.10 to 0.16, and a second deposition step for depositing a second PSG layer with a sputtering deposition ratio of 0.18 to 0.22 after the first deposition step. The first PSG layer has a thickness smaller than that of the second PSG layer. With such two-step deposition method, flower pattern having a dramatically reduced size can be formed without occurrence of clipping or formation of sidewall voids in the resultant gate patterns. Specifically, the formed flower pattern has a height reduced by about 50% and a thickness reduced by about 30%.

Abstract: The present invention discloses a method for inhibiting the electric crosstalk of back illuminated CMOS image sensor. This invention comprises, two ion implanting layers are implanted at the different area of the backside of the pixel unit after the thickness of the backside of CMOS image sensor is reduced. The ion concentrations implanted into the two layers are controlled to decrease progressively from top to bottom. An electric field is formed from top to bottom inside the epitaxial layer. The said electric field absorbs the incident light which arrives at the substrate region outside of the space charge of the photodiode. It reduces the electron diffuses in different pixels. Consequently, it reduces the electric crosstalk of pixels, improves the manufacture process and improve the image quality of the of CMOS image sensor.

Abstract: The present invention provides a method for measuring the interface state density by a conductance technique. In particular, the method comprises: biasing a MOS capacitor structure to be measured in an accumulation region, measuring the MOS capacitor structure under a fixed bias voltage and at predetermined scanning frequencies in the accumulation region by using a Gp-G model, and calculating the values of the series resistor at respective predetermined scanning frequencies to obtain a series resistor model; obtaining an accurate model in an inversion region from the series resistor model varying with the predetermined scanning frequencies obtained in the accumulation region and obtaining the measurement results of interface state according to the accurate model.

Abstract: The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.

Abstract: The present invention provides a method of detecting the transistor mismatch in a SRAM cell. The SRAM cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors. The method comprises: providing two measuring transistors, whose gates are connected to a second word line, sources are connected to the outputs of the bi-stable circuit respectively and drains are connected to two measuring terminals respectively; turning on the measuring transistors and turning off the pass-gate transistors; detecting the voltage-current curve of the two pull down transistors and the two pull up transistors through the measuring transistors at the measuring terminals so as to detect the transistor mismatch in the SRAM cell.

Abstract: A method of forming nickel self-aligned silicide (Ni-salicide) is disclosed, the method including the following steps in the sequence set forth: providing a substrate; forming a gate on the substrate and forming a SiGe source and a SiGe drain beneath a surface of the substrate; growing a silicon epitaxial layer over the SiGe source and the SiGe drain; amorphizing the silicon epitaxial layer; depositing a Ni—Pt layer over the amorphized silicon epitaxial layer; performing a first rapid thermal anneal process to cause Ni—Pt alloy and the amorphized silicon epitaxial layer to react; removing the unreacted Ni—Pt alloy by wet etching; and performing a second rapid thermal anneal process to form a Ni-salicide.

Abstract: A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.