Patents Assigned to Sharp
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Patent number: 6566930Abstract: A level shift circuit for providing an output signal having a swing larger than a swing of an input signal includes a plurality of MOS transistors constituting a circuit operative at a low voltage and a circuit to which a voltage higher than the low voltage is applied. At least one of the plurality of MOS transistors has a gate which receives a signal having a swing corresponding to the swing of the input signal and which is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.Type: GrantFiled: July 14, 2000Date of Patent: May 20, 2003Assignee: Sharp Kabushiki KaishaInventor: Yuichi Sato
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Patent number: 6567073Abstract: In some applications, particularly home and public uses, computers are used concurrently by right and left-handed persons. An ambidextrous computer mouse includes a selector permitting the user to conveniently switch the computer functions activated by the respective mouse buttons for right or left-handed use.Type: GrantFiled: June 9, 2000Date of Patent: May 20, 2003Assignee: Sharp Laboratories of America, Inc.Inventor: Burton L. Levin
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Patent number: 6566753Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers.Type: GrantFiled: April 2, 2002Date of Patent: May 20, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Sheng Teng Hsu
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Patent number: 6566595Abstract: A solar cell having a p-type semiconductor layer and an n-type semiconductor layer made of a first compound semiconductor material, and a semiconductor layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer. The semiconductor layer includes at least a quantum well layer which is made of a second compound semiconductor material and has a plurality of projections of at least two different sizes.Type: GrantFiled: October 29, 2001Date of Patent: May 20, 2003Assignee: Sharp Kabushiki KaishaInventor: Yoshiyuki Suzuki
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Publication number: 20030090455Abstract: A display is backlit by a source having spatially modulated luminance to attenuate illumination of dark areas of images and increase the dynamic range of the display.Type: ApplicationFiled: November 9, 2001Publication date: May 15, 2003Applicant: Sharp Laboratories of America, Inc. a Washington corporationInventor: Scott J. Daly
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Publication number: 20030091075Abstract: The present invention relates to an optical pickup used for an optical recording information instrument such as CD-ROM, CD-R, MO, DVD and the like, and a semiconductor laser device assembled to be incorporated in the optical pickup, as well as to a method for manufacturing said semiconductor laser device. The present invention also relates to a semiconductor laser element comprising a plurality of semiconductor laser chips, which is incorporated in the semiconductor laser device and to a method for manufacturing said semiconductor laser element, especially to an apparatus for accurately bonding and assembling a semiconductor laser element used in manufacturing said semiconductor laser element, such as a semiconductor laser chip die-bonding machine and the like.Type: ApplicationFiled: November 8, 2002Publication date: May 15, 2003Applicant: SHARP KABUSHIKI KAISHAInventors: Hideaki Tatsuta, Hiroshi Chikugawa, Takaaki Horio, Shinji Yudate
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Publication number: 20030093568Abstract: Embodiments of the present invention are directed to a remote desktop communication protocol that includes spatial and temporal compression techniques. Multimedia presentation data is generated at a server from a source. A compression facility modifies the presentation data by both spatially and temporally compressing the presentation data to transmittable data. In some embodiments, a check is performed to ensure that the least amount of data is selected prior to sending the transmittable data to a remote client. The remote client receives the transmittable data and re-constructs the original multimedia presentation data. In some embodiments that use lossy compression, the reconstruction may not exactly re-construct the original multimedia presentation data. Once re-created, the remote client presents the presentation data at the remote client. The presentation data could be audio, video, or other data or a combination of them.Type: ApplicationFiled: November 14, 2001Publication date: May 15, 2003Applicant: Sharp Laboratories of America, Inc.Inventor: Sachin G. Deshpande
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Publication number: 20030091079Abstract: The present invention relates to a semiconductor laser device having a protective coating with a high-reliability formed on an end surface, and to a method for manufacturing the same. According to the present invention, in forming a semiconductor laser device, an electrode comprising Au is patterned so that the electrode does not exist in the vicinity of a light emitting end surface. Thereby, even when an Si film is formed on the light emitting end surface, the Si film is prevented from contacting with the light emitting end surface. In addition, after patterning the electrode, an insulating film (a silicon nitride film) is formed on the electrode for preventing the Si in the protective coating on the end surface from contacting with Au in the electrode, even when the Si film contacts with a surface of the electrode.Type: ApplicationFiled: November 8, 2002Publication date: May 15, 2003Applicant: SHARP KABUSHIKI KAISHAInventor: Makoto Yokota
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Patent number: 6562680Abstract: A method of manufacturing a semiconductor device comprising the steps of: (a) depositing a gate insulating film, a floating gate silicon film, an insulating film between gates, and a control gate silicon film in this order on a silicon substrate and forming thereon a third insulating film; (b) etching said films until the silicon substrate is exposed to form a gate electrode and to open regions for a source and a drain; (c) removing the third insulating film while leaving it on one end or both ends of the gate electrode in the direction of channel length so that the control gate silicon film is partially exposed; (d) forming sidewall spacers on sidewalls of the gate electrode and the third insulating film remaining on the gate electrode; (e) depositing a refractory metal film over the entire surface; and (f) performing a thermal treatment for simultaneous silicidation of the refractory metal film with the exposed control gate silicon film and the silicon substrate to form a metal silicide layer on each of theType: GrantFiled: October 17, 2000Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventor: Keiko Asakawa
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Patent number: 6563734Abstract: In the non-volatile semiconductor memory device of the present invention, its memory region comprises a number of erasable, writable and readable memory blocks in which these functions can be carried out simultaneously. According to the present non-volatile semiconductor memory device, since the memory region is controlled by a partition unit constituting a plurality of memory blocks, the number of objects to be controlled can be reduced relative to the case where the memory region is controlled as individual memory block units. Thus, in a system using the present non-volatile semiconductor memory device, the control thereof can be simplified than in a conventional system.Type: GrantFiled: August 17, 2001Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventor: Masamitsu Taki
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Patent number: 6562693Abstract: There is provided is a semiconductor laser device capable of simplifying fabricating processes with a simple construction and easily mounting two semiconductor laser elements and a monitoring PD on a compact package and a wire bonding method for the semiconductor laser device. There are provided a stem 100 provided with a plurality of lead pins 121 through 124, a sub-mount 160 that is die-bonded onto the stem 100 and has its surface formed integrally with a monitoring PD 140 and two semiconductor laser elements 131 and 132 that are die-bonded onto the sub-mount 160 and have emission light monitored by the monitoring PD 140. A first bonding surface i.e. anode electrode 183 of the monitoring PD 140 and a second bonding surface i.e. end surface 123a of a lead pin 123 that is approximately perpendicular to the first bonding surface are wire-bonded to each other.Type: GrantFiled: March 12, 2001Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventors: Hideki Ichikawa, Mamoru Okanishi, Terumitsu Santo, Toshihiko Yoshida
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Patent number: 6563850Abstract: A light-emitting device includes a first guide layer; a second guide layer; and an active layer interposed between the first guide layer and the second guide layer. The active layer has a multiple quantum well structure including a plurality of quantum well layers and a quantum barrier layer interposed between the adjacent quantum well layers. The first guide layer and the second guide layer are disposed to be adjacent to the quantum well layers. The first guide layer and the second guide layer have a forbidden band width which is larger than a forbidden band width of the quantum well layers. The forbidden band width of at least one of the first guide layer and the second guide layer is smaller than a forbidden band width of the quantum barrier layer.Type: GrantFiled: October 6, 1998Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventors: Mitsuhiro Matsumoto, Masaki Tatsumi
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Patent number: 6562659Abstract: When TCP substrates serving as external circuits are packaged by thermocompression bonding onto input/output terminals on an active-matrix substrate including an a-Se film serving as an amorphous semiconductor layer, a cooling operation is performed by a cooling medium discharging nozzle on at least a part between the a-Se film and a thermocompression bonding part disposed between the TCP substrates and the input/output terminals on the active-matrix substrate. Thus, during the thermocompression bonding, a temperature of the a-Se film is maintained below its crystallizing temperature so as to prevent exfoliation of the amorphous semiconductor film and deterioration in characteristics thereof, upon packaging the external circuits by thermocompression bonding onto the input/output terminals on the substrate including the amorphous semiconductor film.Type: GrantFiled: June 2, 2000Date of Patent: May 13, 2003Assignees: Sharp Kabushiki Kaisha, Shimadzu CorporationInventors: Yoshihiro Izumi, Osamu Teranuma
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Patent number: 6562699Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.Type: GrantFiled: December 21, 1998Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventors: Kotaro Kataoka, Hiroshi Iwata, Masayuki Nakano
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Patent number: 6562703Abstract: A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.Type: GrantFiled: March 13, 2002Date of Patent: May 13, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-Shen Maa, Douglas J. Tweet, Sheng Teng Hsu, Jong-Jan Lee
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Patent number: 6563720Abstract: A switching power supply device is arranged such that a switching of a main switching element is controlled by a control circuit in accordance with output voltage information fed back from the secondary winding side. On this account the switching power supply device has an output voltage being stabilized to be a target value. Moreover, fluctuation of the control is detected only under the light load in accordance with a nonlinear characteristic of a fluctuation detection circuit. A fluctuation in an output of the fluctuation detection circuit is extracted by a differentiating circuit composed of a capacitor and dividing voltage resistors, and the output of the differentiating circuit is superposed on a value of the divided output voltage so as to be fed back. In this manner the fluctuation component, having relatively short change periodicity (like A.C.), of the control fluctuation is superposed on the output voltage information having relatively long change periodicity (like D.C.Type: GrantFiled: March 19, 2002Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventor: Saburou Kitano
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Patent number: 6563174Abstract: In a thin film transistor, a gate insulating film having a first insulating film and a second insulating film is formed on a gate electrode, and a semiconductor layer including ZnO etc. is formed on the second insulating film. The first insulating film is formed by using SiNx having a high insulating characteristic, and the second insulating film is formed by using an oxide (for example, SiO2). This structure improves a crystalline characteristic of the semiconductor layer that constitutes an interface in combination with the second insulating film, and decreases a defective level of the interface between the semiconductor layer and the second insulating film. Further, the second insulating film is constituted of the oxide, so that it is possible to restrain a material for the second insulating film from depriving oxygen of the semiconductor layer.Type: GrantFiled: August 21, 2002Date of Patent: May 13, 2003Assignees: Sharp Kabushiki KaishaInventors: Masashi Kawasaki, Hideo Ohno, Kazuki Kobayashi, Ikuo Sakono
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Patent number: 6563554Abstract: A liquid crystal display is furnished with: a liquid crystal display element having a pair of substrates, to which alignment members are provided to their respective opposing surfaces, and a liquid crystal layer sandwiched by the pair of substrates; an alignment mechanism for providing at least two different director configurations simultaneously on different arbitrary regions used for display in the liquid crystal layer; and a reflection film provided to at least one of the different arbitrary regions showing different director configurations; wherein the different arbitrary regions showing different director configurations are used for a reflection display section for showing reflection display and a transmission display section for showing transmission display, respectively.Type: GrantFiled: June 25, 2001Date of Patent: May 13, 2003Assignee: Sharp Kabushiki KaishaInventors: Masayuki Okamoto, Hajime Hiraki, Seiichi Mitsui
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Patent number: 6563964Abstract: A method and apparatus for digital image downsampling are disclosed with particular application to computer-graphics imagery. The digital image is downsampled non-uniformly in a manner that attempts to minimize aliasing of high-spatial-frequency image information by concentrating deletion paths in lower-spatial-frequency image regions. A spatial frequency estimator compares groups of pixels in order to produce a classification of the image. A path generator and path scorer trace and score potential deletion paths through the image, and the path with the greatest score (i.e., one that provides minimal distortion and aliasing) is selected for pixel removal. A recursor repeats this process until a desired number of image rows and/or columns have been removed.Type: GrantFiled: February 8, 1999Date of Patent: May 13, 2003Assignee: Sharp Laboratories of America, Inc.Inventor: Bryan Severt Hallberg
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Publication number: 20030086292Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.Type: ApplicationFiled: December 17, 2002Publication date: May 8, 2003Applicant: Sharp Kabushiki KaishaInventors: Yoshimitsu Yamauchi, Nobuhiko Ito