Abstract: The present invention provides a method for detecting a size of a pattern made by photolithography, which being applied for detecting a size of a pattern formed on an array substrate of a liquid crystal display including: deriving function layer parameters and position parameters of a detection-pattern; deriving a thickness-profile of the detection-pattern according to the function layer parameters and the position parameters of the detection-pattern; deriving a plane-profile of the detection-pattern according to the thickness-profile of the detection-pattern; proceeding a size-detection to the plane-profile of the detection-pattern.

Abstract: Disclosed is a method for regulating color shift in white balance procedure of a four-color display device. The method includes steps of: obtaining brightness of a white color displayed by a combination according to stimulus values Y of a red sub pixel unit, a green sub pixel unit, a blue pixel unit, and a fourth sub pixel unit; and balancing a white color and one shifting color/two shifting colors/three shifting colors using a weighting factor in case of a two-color balance, a three-color balance, or a four-color balance.

Abstract: A display panel includes, arranged as a stack, a color filter layer, a function layer, and a liquid crystal layer. The function layer has a top and a bottom opposite to each other. The color filter layer is arranged on the top, and the color filter layer includes a blue sub-pixel zone for transmission of blue light. The liquid crystal layer is arranged on the bottom. The bottom is provided with a protrusion structure, and the protrusion structure extends into the liquid crystal layer such that the protrusion structure divides the liquid crystal layer into a first area and a second area. The first area has a projection cast on the color filter layer and having an area covering the blue sub-pixel zone. A liquid crystal cell thickness of the first area is smaller than a liquid crystal cell thickness of the second area. Also provided is a display device.

Abstract: A manufacturing method for a flexible liquid crystal display panel is provided. The method includes steps of: providing multiple light-shielding patterns disposed at a side of the rigid base and arranged as a matrix, providing a second substrate disposed at a side of the multiple light-shielding patterns away from the rigid base or disposed at a side of rigid base away from the multiple light-shielding patterns; aligning a side of the second substrate away from the rigid base with the first substrate, disposing a liquid crystal layer between the first substrate and the second substrate to obtain a liquid crystal cell, wherein the liquid crystal layer includes liquid crystal molecules and polymerizable monomer, and using an ultraviolet light to irradiate the liquid crystal cell at a side of the rigid base away from second substrate to form an organic polymer barrier corresponding to a gap between the light-shielding patterns.

Abstract: Disclosed are a thin film transistor and a display device, which can reduce parasitic capacitance between the first metal layer and the second metal layer so as to improve display quality of a liquid crystal display device. The thin film transistor includes a gate electrode, a gate insulation layer covering the gate electrode, a semiconductor layer formed on the gate insulation layer, and a source electrode and a drain electrode formed on the semiconductor layer. The semiconductor layer has an extension portion, a plane projection of which goes beyond a range of the gate electrode, and the drain electrode covers the extension portion.

Abstract: Disclosed are an array substrate of a thin-film transistor liquid crystal display device and a method for manufacturing the same. The array substrate includes a plurality of data lines, a plurality of dummy data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of groups of pixel units. Each group of pixel units includes an odd-numbered column of first thin film transistors and an even-numbered column of second thin film transistors. First ends and second ends of the dummy data lines are connected respectively to two common voltage electrode lines, which are arranged on the substrate in a transverse direction. The method includes steps of: forming a plurality of gate lines and two common voltage electrode lines; forming a source, a drain, and a plurality of data lines; and forming a plurality of pixel electrodes and a plurality of dummy data lines. A light shielding electrode line provided has good voltage driving uniformity.

Abstract: An array substrate and a liquid crystal display panel are provided. The array substrate includes sub-pixel groups arranged in an array and each including first and second sub-pixels and a third switch assembly. The first sub-pixel includes a first main-zone electrode, a first sub-zone electrode, and a first switch assembly. The second sub-pixel includes a second main-zone electrode, a second sub-zone electrode, and a second switch assembly. The second switch assembly controls conduction of the second main-zone electrode and the second sub-zone electrode. The third switch assembly is connected to the first and second sub-zone electrodes and controls connection and conduction between the first and second sub-zone electrodes to reduce voltages of the first and second sub-zone electrodes. The array substrate helps reduce the number of switch units involved, simplifies the structure of pixels, lowers down fabrication cost, and also increases an aperture ratio of the liquid crystal display panel.

Abstract: Disclosed is a hardware controller of a Nand device, a control method and a liquid crystal display. The hardware controller includes: a bad block management module, configured to manage bad block information of the Nand device, where the bad block information represents a bad block set in the Nand device; a main control module, configured to receive an operation command of a terminal; wherein the operation command is used to indicate a read/write operation on a target block set of the Nand device and a data transmission mode to perform the read/write operation, and the data transmission mode includes at least one of parallel transmission and serial transmission; and a read/write module, configured to skip a block in the Nand device that exists both in the bad block set and the target block set, and perform the read/write operation on remaining blocks in the target block set.

Abstract: Disclosed are a liquid crystal display panel with adjustable viewing angle and a method for adjusting the viewing angle. A pixel unit located in a display area of the liquid crystal display panel includes a main pixel area and a sub pixel area. The main pixel area is horizontally aligned. The sub pixel area is vertically aligned. In the sub pixel area, an upper substrate electrode is arranged beneath the upper substrate and a lower substrate electrode is arranged on the lower substrate. In the sub pixel area, the upper substrate electrode and the lower substrate electrode both have a double layer electrode structure, and bias voltages, under an action of which liquid crystal molecules in the sub pixel area are aligned horizontally, vertically and obliquely, are exerted on the upper substrate electrode and the lower substrate electrode, thereby realizing switching between a narrow viewing angle mode and a wide viewing angle mode.

Abstract: A display panel is provided. The display panel includes a plurality of data lines, a plurality of scan lines, and a plurality of pixel units, wherein each of the plurality of pixel units includes a plurality of sub-pixel units; the plurality of sub-pixels in a same pixel unit are connected to a same data line, and are correspondingly connected to different scan lines. The display panel includes a data driving module and a scan driving module. The data driving module includes a pulse width modulating chip, a gamma correcting chip, a timing control chip, and a data signal generating chip. A display device is also provided.

Abstract: The present disclosure discloses a white OLED device, which includes a substrate, an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer that are disposed to be sequentially laminated; the white OLED device further includes a reflective layer disposed on the electron injection layer or a reflective layer interposed between the substrate and the anode, wherein a material of the reflective layer has a selective reflection function on light having different wavelengths.

Abstract: The invention provides an array substrate and touch display device. The array substrate comprises: a plurality of sub-pixel units arranged in array, a plurality of touch sensing lines and DC power lines; a touch sensing line being provided for each column of sub-pixel units, and a DC power line being provided for each row of sub-pixel units, each sub-pixel unit comprising a photosensitive TFT, and the photosensitive TFT having a floating gate, a source electrically connected to the corresponding DC power line, and a drain electrically connected to the corresponding touch sensing line. The photosensitive TFT absorbs infrared radiation emitted by biological being when touched by biological being, thereby achieving conduction to transmit the voltage on DC power line to touch sensing line to complete touch sensing. The touch function is integrated into sub-pixel unit. No additional touch panel is required, which can reduce production cost and prevent erroneous operation.

Abstract: The invention provides an oxide semiconductor TFT and manufacturing method thereof. The oxide semiconductor TFT comprises: a substrate, a gate on the substrate, a gate insulating layer on the gate and substrate, an oxide semiconductor layer on the gate insulating layer, and a barrier layer on the semiconductor layer, and a source and a drain on the oxide semiconductor layer and gate insulating layer; the oxide semiconductor layer comprising: a channel region and two contact regions respectively located at two sides of the channel region, and the barrier layer being located on the channel region; the channel region comprising a plurality of channel strips spaced apart in a channel width direction, and the barrier layer comprising a plurality of barrier strips respectively corresponding to the plurality of channel strips. The invention can reduce power consumption of the oxide semiconductor TFT and improve and the stability in the winding state.

Abstract: A GOA circuit including a plurality of cascade single-stage GOA circuit units, wherein each of the single-stage GOA circuit units includes: a first pull-down maintaining unit connected to a low power source voltage line and including a first output end; a second pull-down maintaining unit connected to the low power source voltage line and including a second output end; a first compensation unit connected to the first pull-down maintaining unit and configured to connect the first input end to a pre-charging node and a high power source voltage line in response to a first control signal and a second control signal, respectively; and a second compensation unit connected to the second pull-down maintaining unit and configured to connect the second input end to the high power source voltage line and the pre-charging node in response to the first control signal and the second control signal, respectively.

Abstract: Provided is a gate driver for use in a display panel. The gate driver includes a chamfering module configured to receive gate turn-on voltage signals and square wave controlling signals and chamfer the gate turn-on voltage signals in accordance with the square wave controlling signals to generate and output chamfered gate turn-on voltage signals, and a level shifting module configured to receive the chamfered gate turn-on voltage signals, input voltage signals and gate cut-off voltage signals, and output the chamfered gate turn-on voltage signals or the gate cut-off voltage signals in accordance with a voltage value of the input voltage signal. By integrating a chamfering module and a digital adjustable resistance module into a gate driver, it is not necessary to provide a chamfering circuit on a CB of display panel, so as the CB can be miniaturized.

Abstract: A fabrication method of a dye polarizer and a display panel are provided. The fabrication method includes: dissolving a dye mixture and a reactive monomer in a solvent to form a polarization film solution, in which the dye mixture is formed by mixing multiple dichroic dyes and the dye mixture functions to absorb visible light of all wave band; coating the polarization film solution one a base, followed by alignment, to allow the reactive monomer to cure on the base; and repeating the step of forming the dye polarization film for n times to form a dye polarizer including n+1 stacked layers of the dye polarization, where n is a nature number greater than or equal to 2. The display panel includes the dye polarizer that is formed with the fabrication method described above.

Abstract: The present invention provides a display panel and a manufacturing method thereof. The display panel comprises a micro light emitting diode and a thin film transistor electrically coupled to the micro light emitting diode. The micro light emitting diode comprises a P type semiconductor and a N type semiconductor. The P type semiconductor is close to the thin film transistor and the N type semiconductor is configured at one side of the P type semiconductor away from the thin film transistor. One surface of the N type semiconductor away from the P type semiconductor is roughened by a plasma surface treatment process. Since a thickness of the N type semiconductor is larger than a thickness of the P type semiconductor, the crystal quality of material of the N type semiconductor will not be affected as the N type semiconductor is roughened to increase the light efficiency.

Abstract: The present disclosure provides a package structure of an organic light emitting component and a method for manufacturing the same. The package structure includes: a substrate, provided with light emitting pixels; a first barrier layer, arranged on the substrate; a nanoparticle layer, arranged on a portion of the first barrier layer corresponding to a location of the light emitting pixels, wherein the nanoparticle layer is configured to extract light from the light emitting pixels; a buffer layer, arranged on another portion of the first barrier layer where the nanoparticle layer is not set; a second barrier layer, arranged on the nanoparticle layer and the buffer layer. The implementation of the present disclosure allows the light extraction to be applied only on the light emitting pixels. Therefore, it can avoid the waste of material and reduce production cost.

Abstract: Related to is the field of light-emitting panel manufacture, and a light-emitting panel and a method for manufacturing the same are provided, which aim to improve uniformity of light emission of an Organic Light-Emitting Diode (OLED) manufactured by Inkjet Printing (IJP). The light-emitting panel sequentially comprises an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. The method comprises forming a multilayer structure sequentially including an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. According to a size of an edge warp of a light-emitting area of the OLED, a light-shielding layer is designed at a corresponding position of the light-emitting area on the cover glass, and a position of a non-uniform edge is subjected to light-shielding processing, so that the problem of non-uniform light emission caused by the edge warp of the organic light-emitting layer is solved.

Abstract: An image processing method for a display device is provided. The method includes steps of: setting one of the multiple pixels arranged as a matrix of the image to be processed as a pixel to be processed, and using the pixel to be processed as a center and setting remaining pixels as reference pixels; obtaining a maximum brightness value and a minimum brightness value of the brightness of the pixel to be processed and the brightness of each reference pixel; determining a relationship of the brightness relation value between the pixel to be processed and the reference pixels and a preset reference value; when the brightness relation value is greater than the preset reference value, setting the brightness of the pixel to be processed as the maximum brightness value, otherwise setting the brightness of the pixel to be processed as the minimum brightness value.