Abstract: A digital communication transmitter (30) implements a phase constellation (40) which defines a digital communication signal stream that is subsequently compressed (50), thereby introducing distortion into a communication signal (56) transmitted to a complementary receiver (30). The receiver (30) includes a magnitude adjuster (80) which increases the magnitude component of selected phase estimates to at least partially compensate for the compression distortion. The receiver also includes a branch metrics generator (90) having a segment (138) in which branch metric transfer function peaks and valleys are not positioned in receiver phase space to coincide with ideal phase points. The branch metric transfer functions are generated in accordance with a process (102) which bases branch metric calculations upon empirically determined probabilities that characterize system-induced distortions.

Abstract: A time division multiple access digital communications system (12) is provided. The system (12) has a base station (14) configured to generate a receive baud clock (86) and has a receiver (18) and a transmitter (20). The system also has a subscriber unit (16) configured to generate a transmit baud clock (50), and has a transmitter (28) and a receiver (26). The subscriber unit transmitter (28) is configured to transmit a reverse channel signal (54) that incorporates the transmit baud clock (50) as a component thereof. The base station receiver (18) is configured to receive the reverse channel signal (54) from the subscriber unit (16) and produce a phase-error signal (&mgr;′) in response to a phase difference between the transmit baud clock (50) and the receive baud clock (86). The base station transmitter (20) is configured to transmit the phase-error signal (&mgr;′) to the subscriber unit receiver (26).

Abstract: A communication system (10) includes a transmitter (12) which induces in a communication signal (16), a first component of in-phase to quadrature phase (I-Q) imbalance and a receiver (14) which adds a second component of I-Q imbalance. A digital, intermediate frequency (IF) I-Q balancer (38) compensates for the receiver-induced I-Q imbalance so that total distortion is sufficiently diminished and a data directed carrier tracking loop (60) may then perform carrier synchronization to generate a baseband signal (70). An adaptive equalizer (64) within the carrier tracking loop (60) may then effectively operate to compensate for additional distortions, such as the transmitter-induced I-Q imbalance.

Abstract: A digital communications system (10) employs a rotationally invariant phase point constellation (80, 80′, 80″) in a modulator (12) thereof and a corresponding carrier phase acquisition phase locked loop (56, 66, 74, 76, 78) in a demodulator (14) thereof. The phase point constellation (80) is rotationally invariant and the demodulator (14) is able to achieve carrier phase synchronization due at least in part to the inclusion of phase point voids (94) positioned in the phase point constellation (80, 80′, 80″). Pragmatic encoding is employed with differential encoding (28, 64) only on non-convolutionally encoded bits. The phase point constellation (80, 80′, 80″) provides identical codes for convolutionally encoded bits (30) of phase points (84) having equal magnitude that are rotated 90°, 180° and 270° degrees from one another. Specific constellations of 256, 64 and 16 points are disclosed.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) includes a binary data source (32) that provides an input signal stream (34) to a modulator (77,77′). The modulator (77,77′) includes a pulse-spreading filter (76) that filters a phase-point signal stream (50) or a composite signal stream (168) into a modulated signal (74). A constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the modulated signal (74), and a delay element (138) delays the modulated signal (74) into a delayed modulated signal (140) synchronized with the constrained-bandwidth error signal stream (108). A complex summing circuit (110) sums the delayed modulated signal (140) and the constrained-bandwidth error signal stream (108) into an altered modulated signal (112), and a substantially linear amplifier (146) amplifies the altered modulated signal (112) and transmits it as a radio-frequency broadcast signal (26).

Abstract: An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).

Abstract: A phase-noise compensated digital communication receiver (40, 40′, 40″) includes a carrier tracking loop (56) which imposes a transport delay on a carrier tracking loop signal (60) before that signal (60) is fed back upon itself. The carrier tracking loop (56) includes a phase rotator (58) that rotates a down-converted digital communication signal (50) by a phase determined by a phase-conveying signal (72). A carrier tracking loop signal is obtained from the carrier tracking loop and delayed in a delay element (82) by a duration that compensates for the transport delay. A phase rotator (84) then rotates the delayed carrier tracking loop signal through a phase value determined by the phase-conveying signal (72) to obtain an open-loop phase signal (86) from which data are extracted. Different embodiments of the receiver (40, 40′, 40″) are provided to accommodate adaptive equalizer (54) issues.

Abstract: An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).

Abstract: A pragmatic trellis-code modulated digital communications system (20) is provided, in which a demodulator (24) is configured to demodulate a quadrature input signal (62) into an estimation (64) of digital data (54) conveyed thereby. The demodulator (24) includes a branch-metrics generator (74) incorporating a soft-decision generator (82), a delay circuit (86), and a likelihood generator (88); a convolutional encoding circuit; and a hard-decision estimator (78) incorporating a hard-decision generator (98), a selection circuit (104), and an encoding circuit (106). The soft-decision generator (82) generates encoded-bit estimates (ŝ0, ŝ1) from the input signal (62). The delay circuit (86) delays one estimate (ŝ1) relative to the other (ŝ0). The likelihood generator (88) generates likelihoods ({circumflex over (m)}00, {circumflex over (m)}01, {circumflex over (m)}10, {circumflex over (m)}11) thereof.

Abstract: A communication system (10) includes a transmitter (20) having programmable signals (46, 58, 60, 80) which can be used to adjust transmitter-caused quadrature-phase signal imbalances. A receiver (18) of the system (10) is remotely located from the transmitter (20) and generates a signal quality statistic (102, 112) that is monitored in a slow-tracking feedback loop to formulate commands which indicate how to program the programmable signals (46, 58, 60, 80). This receiver (18) performs its signal quality statistic monitoring while a data stream (36) is being extracted from a received communication signal.

Abstract: A digital communication receiver (10) includes a magnitude-based symbol synchronizer (38) which separates complex phase attributes from magnitude attributes. The phase attributes are processed by a phase processor (78) which identifies clock adjustment opportunities. The magnitude attributes are processed by a magnitude processor (76) that generates a phase error estimate signal (82), which in turn drives a clock generator (24) in a phase locked loop (54) to achieve symbol synchronization in a non-data-directed manner. An additional adjustment feedback loop (114, 128) includes a phase error offset generator (52) and operates in conjunction with the phase locked loop (54) to allow the phase locked loop (54) to achieve lock and a robust operating point in spite of distortion in a received input analog signal (12).

Abstract: A phase-noise compensated digital communication receiver (40, 40', 40") includes a carrier tracking loop (56) which imposes a transport delay on a carrier tracking loop signal (60) before that signal (60) is fed back upon itself. The carrier tracking loop (56) includes a phase rotator (58) that rotates a down-converted digital communication signal (50) by a phase determined by a phase-conveying signal (72). A carrier tracking loop signal is obtained from the carrier tracking loop and delayed in a delay element (82) by a duration that compensates for the transport delay. A phase rotator (84) then rotates the delayed carrier tracking loop signal through a phase value determined by the phase-conveying signal (72) to obtain an open-loop phase signal (86) from which data are extracted. Different embodiments of the receiver (40, 40', 40") are provided to accommodate adaptive equalizer (54) issues.

Abstract: A digital communications modulator (10) includes a low speed IC (12) which performs encoding, symbol generation, pulse shaping, interpolation, linearization, and small amounts of frequency tuning. A complex, baseband digital communications signal (34) is output from the low speed IC (12) as a plurality of parallel streams of digital words. In a digital tuner 14 which includes a high speed IC (20), these parallel streams are digitally combined and digitally up-converted to an IF digital data stream (68) that may have a center frequency many times the baud rate. The high speed IC (20) also converts the digital stream to a broadband analog signal (40). The broadband analog signal (40) is processed through an analog band pass filter (42) that removes spectral images, reduces quantization errors, and limits the bandwidth approximately to the baud rate.

Abstract: A node controller (30) within a data communication network (22) provides network access for a digital data stream (32). A processor (42) partitions the digital data stream (32) into a constant data rate component (44) having a predictable data rate and a data packet component (46) having an unpredictable data rate. The constant data rate component (44) is then transferred over a first portion (74) of a network data stream (26) reserved for a circuit transmission protocol, and the data packet component (46) is packetized and transferred over a second portion (76) of the network data stream (26) reserved for a packet transmission protocol.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies

Abstract: A digital communication system (20) communicates using a polar amplitude phase shift keyed (P-APSK) phase point constellation (70, 70', 70"). Pragmatic encoding is accommodated using the constellation (70, 70', 70") to simultaneously communicate both encoded and uncoded information bits (69, 51). The constellation (70, 70', 70") has an even number of phase point rings (74) and equal numbers of phase points (72) in ring pairs (75, 76, 77). Encoded information bits (69) specify secondary modulation and uncoded information bits (51) specify primary modulation. The constellation (70, 70', 70") is configured so secondary sub-constellations (78) include four phase points (72) arranged so that two of the four phase points (72) exhibit two phase angles at one magnitude and the other two of the four phase points (72) exhibit phase angles that are at another magnitude. The difference between the phase angles at different magnitudes within a secondary sub-constellation (78) is constant.

Abstract: A communication system (11) uses concatenated coding in which an inner code is configured to match the needs of an outer code. The inner code is implemented through a pragmatic trellis coded modulation encoder (18) and decoder (34). A parser (50) of the encoder (18) distributes fewer than one user information bit per unit interval (66) to a convolutional encoder (58) which generates at least two convolutionally encoded bits for each user information bit it processes. Exactly one of the convolutionally encoded bits is phase mapped (56) with at least two user information bits during each unit interval (66). The decoder (34) detects a frame sync pattern (48) inserted into the user information bits to resolve phase ambiguities. Phase estimates are convolutionally decoded (100) to provide decoded data estimates that are then used to selectively rotate the phase estimates prior to routing the phase estimates to a slice detector (118).

Abstract: Different subscriber units (14) transmit different burst signals to a base station (12) on a common frequency to which a base station demodulator (64) is already synchronized. The base station (12) transmits constant values .alpha. and .eta., where .alpha. is multiplied by a base station reference frequency to achieve a base station transmitting frequency, and .eta. is multiplied by the reference frequency to achieve the base station (12) receiving frequency. A subscriber unit (14) synchronizes to the base station transmitting frequency. As a result of the synchronization process, the subscriber unit (14) determines a value .mu., which, when multiplied by a subscriber unit reference frequency, achieves the subscriber unit synchronization frequency. The subscriber unit then determines a value .gamma., which is proportional to .eta. and .beta. and inversely proportional to .alpha.. The subscriber unit reference frequency is multiplied by .gamma.

Abstract: A communication system (10) includes a rotationally invariant pragmatic trellis coded modulator (18) and demodulator (34). The modulator (18) partitions information bits (20) into primary (42) and secondary (44) data streams. The secondary data stream (44) is convolutionally encoded (70) then fed to the LSB of a phase mapper (76). The phase mapper (76) is arranged so that all pairs of adjacent phase data are generated from pairs of opposing polarity LSB inputs. The primary data stream (42) is differentially encoded through a dual channel differential encoder (50). The demodulator (34) convolutionally decodes (90) the secondary stream, then re-encodes (96) secondary stream estimates. The re-encoded secondary stream estimates are used to remove (102) the secondary modulation from phase value estimates. Adjusted phase value estimates are phase demodulated (104) and differentially decoded using a dual channel differential decoder (106).

Abstract: A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies