Abstract: An interference-tolerant spread-spectrum receiver (20) includes an FIR (finite impulse response) filter network (32) and a correlator/detector (34). The filter network (32) contains a pair of FIR filters (36) substantially identical to each other. A signal passes directly into the first filter (36'), but is delayed a predetermined amount of time before passing into the second filter (36"). Each of the filters (36) contains means for sampling (62) and windowing (70) the signal in the time domain; transforming (118) the signal to the frequency domain; limiting (130) and despreading (160) the signal in the frequency domain; and transforming (168) the signal back to the time domain. The signal from the first filter (36') is delayed the predetermined amount of time to resynchronize signals from both filters (36), which signals are then combined into a single signal. The combined signal is then passed into the correlator/detector (34), which determines the presence or absence of a spread-spectrum signal.

Abstract: A local multipoint data distribution system (10) simultaneously accommodates many communication sessions occurring at a wide variety of data rates. space surrounding cell sites (12) is partitioned into sectors (16), and the spectrum is allocated to the cell sites (12) so that adjacent sectors (16) use different spectrum portions, but the entire spectrum is reused numerous times at each cell site (12). A time diversity scheme allocates different numbers of time slots (54) to different calls. Time slot identifiers are assigned in contiguous blocks in an assigned numbering system (56). The time slot identifier assignments are translated into a counted numbering system (58) which causes the time slots (54) for any call to be distributed throughout a frame (48) and interleaved with time slots (54) assigned to other calls.

Abstract: A digital data receiver includes a tunable analog matched filter circuit having a variable bandwidth responsive to the bit error rate (BER) of the decoded data. The bandwidth of the analog filtering circuit is controlled by a tuning control signal that includes a coarse tuning signal combined with a fine tuning signal. The coarse tuning signal is generated by a frequency-to-current converter and the fine tuning signal is generated by a current-scaling digital-to-analog converter (DAC). The DAC input signal is produced by a DAC control circuit that includes a BER comparator and a DAC control state machine. The BER comparator determines whether the BER has improved or degraded in response to a previous tuning command. To optimize the BER in the decoded data signal, the state machine increments or decrements the value of the fine tuning signal, which in turn alters the filter bandwidth.

Abstract: A communication system (11) uses concatenated coding in which an inner code is configured to match the needs of an outer code. The inner code is implemented through a pragmatic trellis coded modulation encoder (18) and decoder (34). A parser (50) of the encoder (18) distributes fewer than one user information bit per unit interval (66) to a convolutional encoder (58) which generates at least two convolutionally encoded bits for each user information bit it processes. Exactly one of the convolutionally encoded bits is phase mapped (56) with at least two user information bits during each unit interval (66). The decoder (34) detects a frame sync pattern (48) inserted into the user information bits to resolve phase ambiguities. Phase estimates are convolutionally decoded (100) to provide decoded data estimates that are then used to selectively rotate the phase estimates prior to routing the phase estimates to a slice detector (118).

Abstract: A digital demodulator (10) reads symbol samples into a memory buffer (38) that can be played forward and backward into a phase locked loop (48). During an initial non-data directed symbol timing estimating phase (56) the demodulator (10) achieves an approximate frequency synchronization and starts to achieve phase synchronization on an incoming stream of symbols. During a first forward readout pass (58) of stored samples, the phase locked loop (48) begins the frequency and phase convergence. During subsequent pass (60) using a reverse readout of stored samples, phase locked loop (48) continues to converge toward zero phase error. Then another forward pass (66), phase locked loop (48) achieves usable frequency and phase synchronization of carrier and begins valid data extraction.

Abstract: A communication system (10) includes a rotationally invariant pragmatic trellis coded modulation (PTCM) encoder (18) and decoder (34). The PTCM encoder (18) partitions information bits (20) into primary (42) and secondary (44) data streams. A pilot bit (56) is inserted into the secondary data stream (44) during each frame (46). The secondary stream (44) then receives rate 1/2 convolutional encoding (60) that is punctured to a rate of 9/16. The primary data stream (42) is differentially encoded (50). The encoded primary and secondary streams are concurrently phase mapped (70) using an 8-PSK constellation so that an effective code rate of 5/6 results. The PTCM decoder (34) convolutionally decodes (84) the secondary stream, then re-encodes secondary stream estimates using a systematic, transparent convolutional encoder (88). The pilot bit is evaluated (92) in the re-encoded symbol estimates (90) to detect and correct any secondary stream inversion that may have occurred due to phase ambiguity.

Abstract: A signal converter (20) processes an incoming digital data stream (24) to produce an analog signal (26). A pulse shaping network (28) is configured to receive the incoming digital data stream (24) and generate a plurality of subset data streams (30). A precompensation network (32) then crosscouples the subset data streams (30) to produce crosscoupled data streams (38). Each of crosscoupled data streams (38) are then converted by respective ones of digital to analog converters (22) to produce intermediate analog signals (44). The intermediate analog signals (44) are summed by an operational amplifier (46) to produce the analog signal (26). The precompensation network (32) can be combined with the pulse shaping network (28) by using a common look-up memory element (70) to perform both functions.

Abstract: A local multipoint data distribution system (10) simultaneously accommodates many communication sessions occurring at a variety of data rates. Space surrounding cell sites (12) is partitioned into sectors (16), and the spectrum is allocated so that adjacent sectors (16) use different spectrum portions, but the entire spectrum is reused numerous times. A time diversity scheme allocates different numbers of time slots (54) to different calls. Time slot identifiers are assigned in contiguous blocks in an assigned numbering system (56). The time slot identifier assignments are translated into a counted numbering system (58) which causes the time slots (54) for any call to be distributed throughout a frame (48) and interleaved with time slots (54) assigned to other calls. Data communications use a common modulation format and a modulation order that is specifically adapted to a particular call.

Abstract: A pulse width modulation (PWM) circuit translates digital data into an analog signal. The PWM circuit includes at least a digital counter, a significance reverser, and a comparator circuit. The significance reverser reverses the relative order of significance of at least two bits in the count words generated by the counter. The comparator determines whether the magnitude of a digital input word is greater than the magnitude of the reversed order count word. The PWM circuit produces a high output when the magnitude of the input word is greater than the magnitude of the reversed order count word and a low output when the magnitude of the input word is not greater than the magnitude of the reversed order count word. The analog output produced by the PWM circuit includes a number of pulses evenly distributed during the count cycle of the counter, and the input word indicates a duty cycle for the analog output.

Abstract: A digital communication receiver (#10) takes one complex sample (#20) of a baseband analog signal (#12) per symbol. A rectangular to polar converter (#44) separates phase attributes of the complex samples from magnitude attributes during coarse symbol synchronization (#28). A phase processor (#48) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (#46) influences symbol timing only during clock adjustment opportunities. The magnitude processor (#46) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities during coarse symbol synchronization (#28).

Abstract: A digital data receiver includes tunable analog components having variable parameters that are responsive to the bit error rate (BER) of the decoded digital data. The analog components include a quadrature generator having a tunable phase shifter, an analog filter having a tunable bandwidth, a tunable magnitude equalizer circuit, a tunable group delay equalizer circuit, and an amplifier having an adjustable gain. The tunable components are controlled by tuning control signals that incorporate digitally-produced fine tuning signals. The digital tuning signals are altered in accordance with realtime changes in the BER.

Abstract: A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.

Abstract: A selectable demodulator (32) operates in the phase domain to implement a coherent demodulation path (40) and a differentially coherent demodulation path (42). The coherent path (40) includes a differential encoder circuit (46) to produce coherently demodulated differential data. Magnitude converters (62, 62') convert phase errors in each path into magnitude values. A comparison circuit (66) compares magnitude values from the two paths (40, 42) and selects the path encountering the least phase error. A selection circuit (60) provides data codes demodulated in accordance with the selection.

Abstract: Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops.

Abstract: A communication system (10) includes a modulation section (12) and a demodulation section (14). The modulation section (12) performs frequency modulation in accordance with a frequency trajectory signal (28, 30, 32). An intersymbol interference (ISI) prediction filter (20) adjusts the amplitude of the frequency trajectory signal (28, 30, 32) in response to data code (16) sequences being conveyed over a plurality of symbols (18). More frequent data changes in the sequence of the data codes (16) lead to greater amplitudes in the frequency trajectory signal. The demodulation section (14) applies a distorted phase signal to a decision circuit (38). The distorted phase signal conveys a received phase (46) that includes ISI. Due to the equalization applied by the ISI prediction filter (20), the received phase (46) approximates a target phase (40, 42) in spite of the ISI.