Abstract: A communication system includes a front-end multi-throw switch, a back-end multi-throw switch, multiple filters and a switch controller. The front-end multi-throw switch includes front-end throws and a front-end pole. The front-end pole is coupled to a receive channel or a transmit channel. The front-end pole is switchably coupled to one of the front-end throws. The back-end multi-throw switch includes back-end throws and a back-end pole. Each of the back-end throws is associated with a corresponding one of the front-end throws. The back-end pole is coupled to the receive channel or the transmit channel. The back-end pole is switchably coupled to one of the back-end throws. The one of the back-end throws corresponds to the one of the front-end throws. The filters are interposed between the front-end multi-throw switch and the back-end multi-throw switch. Each of the filters has a first port coupled to one of the front-end throws and a second port coupled to one of the back-end throws.

Abstract: A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.

Abstract: A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.

Abstract: Methods and apparatus for providing connection packages for high-speed integrated circuits (“ICs”) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density IC's input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher-clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A quadrature ring oscillator for high clock-rate applications is disclosed. A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers to provide consistent oscillation even at high clock rates. One stage of the quadrature ring oscillator comprises a first resonating element having an input and an output, and a first variable summer having L and P inputs and an output, with its L input being connected to the output of the first resonating element. The output of the first variable summer is connected to the input of the first resonating element The first variable summer may generate its output at a first phase by combining the L and P inputs. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and an output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element.

Abstract: A broadband power amplifier module for high bit-rate SONET/SDH transmission channels, such as OC-192 and OC-768 applications. The power amplifier module, or also frequently referred to as modulator driver module, comprises amplifiers connected in series to amplify an input signal. A bias tee circuit is incorporated into the power amplifier module by connecting a conical shape inductor between the output stage of the amplifiers and the supply voltage and connecting a pair of blocking capacitors also at the output stage of the amplifiers. The conical shape inductor is adapted to provide high impedance over the entire bandwidth. The capacitors are adapted to provide high self-resonant frequency that is approaching or exceeding the bandwidth frequency. A power detection circuit can also be incorporated into the power amplifier module at the output stage of the amplifiers. The power detection circuit has a voltage divider circuit connected between the output stage and a ground supply.

Abstract: Methods and apparatus for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels are disclosed. The invention includes a phase detector for comparing a data signal and a clock signal, a one shot unit for detecting a data transition, an XOR, a filter, a main charge pump, a compensating charge pump for producing additive or compensating current, and a VCO for generating the clock signal. The phase detector includes multiple D-flip flops. The one shot unit includes a delay unit and an AND gate. The filter includes a resistor, a capacitor and a negative resistance amplifier. The main charge pump includes differential inputs, double outputs, cross-quading resistors, differential NPN input transistors, and a current source. The compensating charge pump includes differential NPN input transistors and a current source.

Abstract: A superconducting gyroscope of the present invention includes a circuit which produces a magnetic field which is synchronous with the rate of rotation experienced by the gyroscope, a sensing circuit for converting the synchronous magnetic field into an electric signal, a first shield made of superconducting material for performing shielding of external stray fields, and a second shield disposed inside the first shield and made of superconducting material for expelling trapped residual magnetic flux. The synchronous magnetic field producing circuit includes a magnetic core shaped in a toroid with an air gap. The magnetic core may alternatively be formed in meandering shape by a plurality of separate magnetic core members with a plurality of air gaps therebetween. The sensing circuit includes at least one SQUID which can be directly coupled to the magnetic core.