Abstract: This invention provides a method of pixel data compression in which sets of adjacent pixels are compressed in a manner which is sometimes lossy but which reserves the greatest loss of accuracy for circumstances where loss is masked by high frequency components of the original pixel data.

Abstract: Apparatus and methods, and computer program products are disclosed that accepts time-stamped information and feeds that information to a buffered system that consumes the information. The invention accepts an initial interval of the time-stamped information and when a pre-fill limit is reached, starts consumption of the data. The pre-fill limit is determined by monitoring the time stamp on the data that is ready to be consumed and the time stamp of data that has just been accepted. The difference between these time stamps provides an interval that represents the amount of time related to the data associated with the time-stamped information. Once the interval exceeds a pre-fill limit, the invention allows the buffered time-stamped information to be consumed. As the time-stamped information is consumed, the invention monitors the interval (other embodiments use the time stamp of data that is in the process of being consumed, or data that has just been consumed).

Abstract: The present invention increases the difficulty of reverse engineering sensitive information protected by an encryption algorithm by increasing the difficulty associated with tracing the code that generates the key or the encryption algorithm. This is accomplished by generating the key, used to encrypt and decrypt the sensitive information, as a function of the program instruction values of the procedures used to generate the key and perform the decryption of the sensitive information. Thus, if the key generation code or the decryption code is modified (such as (but without limitation) by placement of a breakpoint, a trace function, or a halt instruction in the code) the resulting key will be different from the key used to encrypt the sensitive information and the decryption attempt will fail.

Abstract: The present invention provides a method for matching the rate of presentation of digital video data at a receiver/client with the rate the server is serving the data without the need of a voltage control oscillator or other hardware. An embodiment of the invention compares the presentation time at the receiver with the server elapsed time estimated from timestamp values on the served data. When the presentation time and the server elapsed time differ by an unacceptably large amount, an adjustment is made to the audio data stream to re-synchronize the presentation time with the elapsed time, which effectively also synchronizes the overall presentation rate with the overall server rate. The video data stream is then synchronized to the adjusted audio stream. The video data stream and audio data stream are converted to analog signals for presentation.

Abstract: A method and system for capturing live video signal data using bufferless data compression is disclosed. Live video signal data is vertically scaled. A 4:2:2 to 4:2:0 color format conversion is performed simultaneous with the vertical scaling step. A one-dimensional bufferless discrete cosine transform is performed on the scaled live video signal data to create a plurality of scaled DCT coefficients. Each of the plurality of scaled DCT coefficients are then Huffman coded. Each of the Huffman encoded DCT coefficients may then be sent via a USB interface to a USB bus.

Abstract: An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen (by means of an a multiplexer output) at the same time. An alignment detector may attempt to align two known signals (such as a VGA sync signal and a signal generated for this purpose), and may adjust a set of time delays in the analog chromakey mixer until the time difference between the first and second video signals falls below a threshold.

Abstract: A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.

Abstract: An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command interface has a set of registers that are made available to the CPU for reading and writing, even if there are no such physical registers available in the device. The DSP also performs tasks in addition to audio-output, even though the audio-output device is required to respond immediately to commands from the CPU. The audio-output device has a DSP for interpreting and executing commands received from the CPU, a local memory for storing data input to or output from the DSP, a bus-interface (BIF) element for coupling the DSP and memory to a system bus, and a direct memory access (DMA) element for transferring data between the local memory and the system bus.

Abstract: An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen (by means of an a multiplexer output) at the same time. An alignment detector may attempt to align two known signals (such as a VGA sync signal and a signal generated for this purpose), and may adjust a set of time delays in the analog chromakey mixer until the time difference between the first and second video signals falls below a threshold.

Abstract: A method and system for capturing live video signal data using bufferless data compression is disclosed. Live video signal data is vertically scaled. A 4:2:2 to 4:2:0 color format conversion is performed simultaneous with the vertical scaling step. A one-dimensional bufferless discrete cosine transform is performed on the scaled live video signal data to create a plurality of scaled DCT coefficients. Each of the plurality of scaled DCT coefficients are then Huffman coded. Each of the Huffman encoded DCT coefficients may then be sent via a USB interface to a USB bus.

Abstract: A method and system for capturing live video signal data using bufferless data compression is disclosed. Live video signal data is vertically scaled. A 4:2:2 to 4:2:0 color format conversion is performed simultaneous with the vertical scaling step. A one-dimensional bufferless discrete cosine transform is performed on the scaled live video signal data to create a plurality of scaled DCT coefficients. Each of the plurality of scaled DCT coefficients are then Huffman coded. Each of the Huffman encoded DCT coefficients may then be sent via a USB interface to a USB bus.

Abstract: An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command interface has a set of registers that are made available to the CPU for reading and writing, even if there are no such physical registers available in the device. The DSP also performs tasks in addition to audio-output, even though the audio-output device is required to respond immediately to commands from the CPU. The audio-output device has a DSP for interpreting and executing commands received from the CPU, a local memory for storing data input to or output from the DSP, a bus-interface (BIF) element for coupling the DSP and memory to a system bus, and a direct memory access (DMA) element for transferring data between the local memory and the system bus.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.

Abstract: An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen (by means of an a multiplexer output) at the same time. An alignment detector may attempt to align two known signals (such as a VGA sync signal and a signal generated for this purpose), and may adjust a set of time delays in the analog chromakey mixer until the time difference between the first and second video signals falls below a threshold.

Abstract: Methods of encoding and decoding data in variable-length data structures, such as that found in motion picture data. Data in an MPEG standard format may be encoded in a format which is not easily subject to unauthorized copying, but which may be easily displayed in a real-time video and audio display. The encoded data may be less subject to errors in data distribution and data storage than known methods of data transformation. Encoded data may be multiplexed with non-encoded data, or may be multiplexed with data encoded by another technique, in such manner that recovery of the original motion picture video and audio may still be achieved in real time. The degree of encoding may take on differing values, so that, for example, all motion picture data is encoded for one video clip, while only some of data is encoded for a second video clip.

Abstract: Apparatus and a method is disclosed for mixing animation sequences with computer graphics information for presentation on a computer display screen. The animation sequences may be stored in compressed format in a standard storage medium. An animation sequence generator retrieves these compressed animation sequences, decompresses them into pixel information, and sends them to a single line store for synchronization with the computer graphics pixel information. Pixels from the animation sequences and from the computer graphics generator are mixed, windowed and overlaid in a digital mixer. The output of the digital mixer is sent to a visual display system such as a video digital-to-analog converter driving a computer display monitor.

Abstract: A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same memory buffer. A display controller and a video MPEG engine contend for access to a DRAM memory buffer controller, and have their relative priorities set so that the video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when the display controller is reading from that same memory buffer, and to write to the memory buffer at a relatively fast speed during a time period when the display controller is not reading from the memory buffer. The relatively slow speed is preferably much slower than the reading speed of the display controller, while the relatively fast speed is preferably much faster than the display controller.

Abstract: An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command interface has a set of registers that are made available to the CPU for reading and writing, even if there are no such physical registers available in the device. The DSP also performs tasks in addition to audio-output, even though the audio-output device is required to respond immediately to commands from the CPU. The audio-output device has a DSP for interpreting and executing commands received from the CPU, a local memory for storing data input to or output from the DSP, a bus-interface (BIF) element for coupling the DSP and memory to a system bus, and a direct memory access (DMA) element for transferring data between the local memory and the system bus.

Abstract: A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus. The coprocessor is disposed to receive data written from the master device, perform a coprocessing function on that data, and respond to a read data command from the master device with processing results. The coprocessor uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus. A general purpose computer system comprises a central processor and memory coupled to a PCI bus, a graphics processor and graphics memory coupled to the PCI bus, and a coprocessor coupled to the graphics processor and graphics memory.