Abstract: A wireless transceiver includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a wireless protocol, a processing module that executes the plurality of operational instructions, and a first interface module. The second integrated circuit includes a second interface module that couples data to and from the first interface module, an RF transceiver that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first interface module via the second interface module, and that generates data based on the second baseband signal to send to the first interface module via the second interface module.

Abstract: A system includes a computer having a device driver. The device driver includes a detection module to detect an audio input. The device driver includes a selection module to send the audio input to audio hardware after detection of the audio input. The device driver also includes an emulation module to send hardware emulation information to an operating system audio application to replace feedback data received at the device driver from the audio hardware and sent from the device driver to the operating system audio application.

Abstract: A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol.

Abstract: A wireless handset or wireless headset includes a Bluetooth transceiver that is coupleable to an external Bluetooth compatible device, that sends the first audio data to the external Bluetooth compatible device and that receives the second audio data from the external Bluetooth compatible device. The Bluetooth transceiver includes a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a Bluetooth protocol, a processing module that executes the plurality of operational instructions, and a first interface module.

Abstract: A system and method for providing an audio source to an audio hardware device is disclosed. The system includes a detection module to detect a first audio input and a selection module to selectively provide the first audio input at an audio output to an audio device after the first audio input has been detected. The system also includes an emulation module to provide hardware emulation information corresponding to feedback data of the audio device after the first audio input has been detected.

Abstract: A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.

Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.

Abstract: A system and method for processing a digital audio signal is disclosed. The system includes an input to receive a digital audio signal and a first output to provide a first digital output signal. The digital audio signal has a first fidelity characteristic and the first digital output signal has a second fidelity characteristic. The second fidelity characteristic is determined in response to security information extracted from the digital audio signal. The first digital output signal is provided to a digital to analog converter.

Abstract: An infrared data receiver includes an infrared detector for generating a received signal from an infrared input signal. A sampling module generates a sequence of sampled data from the received signal. A plurality of processing modules are included, wherein each processing module is capable of detecting and decoding data in at least one of a plurality of data formats. Each processing module analyzes the sequence of sampled data for its particular data formats. When a processing module detects one of its data formats, it generates a detection signal and decodes the sequence of sampled data into decoded data. A controller module receives the detection signal from one of the plurality of processing module, and disables the other ones of the plurality processing modules.

Abstract: Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: Systems and method to compress digital video based on human factors expressed as a desirability score are provided. A particular method includes passing a digital input signal through a pulse-width modulator and passing an output of the pulse-width modulator through a power switching device. An output of the power switching device has a plurality of pulses. The method includes receiving the output of the power switching device at a first input of a comparator and receiving a reference voltage at a second input of the comparator. The method includes determining a net signal based on an output of the comparator and determining a timing error signal based on the net signal and the digital input signal. The method also includes adjusting the digital input signal to compensate for harmonic distortion based at least in part on the timing error signal.

Abstract: A method and apparatus for processing content data includes processing that begins by receiving modulated data via a channel that couples a content display device to a content processing device. The processing continues by introducing the content data onto the channel and separating the modulated data from the content data. The processing then continues by retrieving data from the modulated data, wherein the content display device modulates the modulated data. The processing continues by processing the data to produce presentation information. The processing then continues by processing the content data for presentation on the external content display device based on the presentation information.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A handheld audio system includes a radio signal decoder integrated circuit (IC) and a digital audio processing integrated circuit. The radio signal decoder integrated circuit produces a digital left channel signal and a digital right channel signal from a received radio signal in accordance with an enable signal and also produces a system clock. The digital audio processing integrated circuit includes a DC-to-DC converter and a processing module. The DC-to-DC converter is operably coupled to produce at least one power supply voltage based on the system clock. The processing module is operably coupled to produce the enable signal when the at least one power supply voltage has reached a desired level and to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.

Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.

Abstract: A system and method of synchronizing to a frame sequence in an input signal includes tolerating data errors within certain error thresholds. In an embodiment, a Hamming distance between data included in a frame alignment word field and an expected value is compared to a predetermined Hamming distance to determine a synchronization event.

Abstract: A method and system for utilizing multiple speakers in a portable electronic device is disclosed. The method includes receiving an input at a user interface of a portable electronic device, switching a first and second speaker in a stereo configuration to a mono configuration by routing a first digital to analog converter (DAC) output to both the first and second speaker in response to the input and coupling a third speaker to a second DAC to receive a first audio signal that is responsive to the input. The system includes a first digital to analog converter coupled to a first speaker, a second DAC coupled to a second speaker, and a third speaker. The system further includes switching logic coupled to the first and second DACs. The switching logic is responsive to an input signal provided by a user interface of a portable device. In response to an input signal from the user interface, the switching logic couples the first and second speakers to the first DAC and the third speaker to the second DAC.

Abstract: A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to input multimedia data received from either the multimedia module or the high-speed interface. The output multimedia data is provided to either the multimedia module or the high-speed interface. An on-chip DC-to-DC converter converts a battery voltage into a supply voltage that is coupled to the multimedia module, the high-speed interface, and/or the processing module.

Abstract: A system and method for decimating a digital signal is disclosed. The system includes an input to receive digital data, a control input to receive a desired decimation rate, and an integrator stage responsive to the input. The system also includes a variable rate down sampling module responsive to the integrator stage and a differentiator stage responsive to the variable rate down sampling module. The down sampling module has a decimation rate that is dynamically adjustable based on the desired decimation rate.

Abstract: A digital microphone interface includes a phase generator for generating a phase signal. A clock generator produces a digital microphone clock at a selected frequency based on the frequency select signal, and supplying the digital microphone clock to a digital microphone. A first data latch, operably coupled to the phase generator, produces a stream of first data from a first channel of the digital microphone, based on a phase select signal and the phase signal.