Abstract: A wireless handset includes a long range wireless transceiver for selectively providing an inbound communication and an outbound communication through a wireless telephone network. A battery monitor module monitors a remaining power of a battery and produces a control signal when the remaining power compares unfavorably to a reserve power threshold. A processing module allows an outbound communication to an allowed recipient when the control signal is asserted, and prohibits an outbound communication to a disallowed recipient when the control signal is asserted.

Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.

Abstract: Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: A touch screen driver includes a conditioner module for conditioning a first input/output port of a touch screen. The conditioner module includes a precharge module for charging the first input/output port to a precharge voltage in response to a precharge signal, and a pull-up module for maintaining the precharge voltage for detecting a touch event.

Abstract: A computer audio system and method is disclosed. The system includes an input to receive a digital audio input signal and a splitter to split the digital audio input signal into a plurality of digital audio signals. The system also includes a plurality of digital signal processing software modules corresponding to a detected number of hardware audio interfaces.

Abstract: A demodulator system and method is disclosed. In an embodiment, the demodulator system can include a Coordinate Rotation Digital Computer (CORDIC) mixer to mix a first signal substantially to baseband using a first input frequency and to mix a second signal substantially to baseband using a second input frequency. In another embodiment, the demodulator system can include a phase detector to receive a pilot signal and to generate a control signal to adjust a decimation rate based on the pilot signal. In another embodiment, the demodulator system can include a symbol decoder to determine a symbol from a phase signal.

Abstract: A method of charging a battery includes applying a charging current from a semiconductor device to the battery during a first battery charging time period. The method also includes measuring a charging voltage level at the battery during the first battery charging time period. During a non-charging voltage measurement time interval, the method includes temporarily stopping application of the charging current from the semiconductor device to the battery and measuring a non-charging voltage level at the battery while the charging current is not being applied to the battery.

Abstract: Systems and methods to control one time programmable (OTP) memory are included. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: A system and method for decoding a received television signal is disclosed. The system includes an input to receive a digital audio signal and a digital variable deemphasis module to modify the amplitude of the digital audio signal based on a plurality of variable coefficients. The system also includes an exponential digital root mean square (ERMS) detector to provide level detection of the digital audio signal. The plurality of variable coefficients of the digital variable deemphasis module are digitally computed based on an output of the digital ERMS detector.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of laser fuses represents error correction coding data that corresponds to the unique identifier. The unique identifier can be a digital rights management identification. Also, the error correction coding data is configured for use by a Reed-Solomon error correcting method to correct the unique identifier. Alternatively, the error correction coding data is configured for use by a cyclic redundancy check method.

Abstract: A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

Abstract: Disclosed is a digital audio device that includes a communications port to communicatively connect the device to a server. The device also includes a unique identifier to identify the device. The device also includes a controller to allow transfer of digital audio files from the server. The digital audio files contain interleaved data selected by the server based on the unique identifier. The device also includes a decoder to decode the interleaved data and a data store to store at least one of the digital audio files and the interleaved data.

Abstract: An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

Abstract: An audio signal processing system and method is disclosed. In a particular embodiment, the audio signal processing system includes a first electrical path responsive to a power supply of an audio amplifier. The first electrical path can include a low pass filter to filter a direct current (DC) component of the power supply and a first analog-to-digital converter (ADC) responsive to the low pass filter. The audio signal processing system also includes a second electrical path responsive to the power supply. The second electrical path can include a high pass filter to filter an alternating current (AC) component of the power supply and a second ADC responsive to an output of the high pass filter. The audio signal processing system includes compensation logic to modify an audio signal based on a first signal generated from the first electrical path and a second signal generated from the second electrical path.

Abstract: A receiver includes a mixing module for mixing an input signal by at least one mixing sequence to produce a mixed signal. The mixed signal is filtered to produce a first filtered signal. A first downsampler downsamples the first filtered signal to produce a first decimated signal, wherein the decimation period is not a multiple of the mixing period.

Abstract: A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.

Abstract: A handheld audio system having a radio signal decoder that includes a method for adjusting a system clock. Adjusting the system clock includes receiving a signal at a rate of a receive clock, wherein the signal includes data at a transmit rate. An error term is determined between the receive rate and the transmit rate. Based on the receive clock and the error term, where the error term is non-zero, a clock signal is generated.

Abstract: A system and method for determining a clock rate of a digital phase lock loop is disclosed. The system includes a first input to receive a first clock signal, an output to provide a second clock signal, and a dividerless initial clock rate determination module to calculate an initial clock rate value based on an reciprocal of a pulse length of the first clock signal. In a particular embodiment, the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.

Abstract: Systems and method to compress digital video based on human factors expressed as a desirability score are provided. A particular method includes passing a digital input signal through a pulse-width modulator and passing an output of the pulse-width modulator through a power switching device. An output of the power switching device has a plurality of pulses. The method includes receiving the output of the power switching device at a first input of a comparator and receiving a reference voltage at a second input of the comparator. The method includes determining a net signal based on an output of the comparator and determining a timing error signal based on the net signal and the digital input signal. The method also includes adjusting the digital input signal to compensate for harmonic distortion based at least in part on the timing error signal.