Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A method for “booting up” a multiple function device that involves first detecting the activation of the multiple function device. A 1st boot algorithm, retrieved from read-only memory, is executed to identify the location of a 2nd boot algorithm. The 2nd boot algorithm, retrieved from a specified location based on the booting inputs, is verified for executability. When the 2nd boot algorithm is executable, it is executed to retrieve the functional algorithms that configure the multiple function device in the desired configuration. When the 2nd boot algorithm is not executable, and the multiple function device is operably coupled to a host, the correct functional algorithm or a default functional algorithm is downloaded and executed to configure the multiple function device. When an executable functional algorithm cannot be retrieved from memory or the host, the multiple function device powers down after a predetermined amount of time.

Abstract: Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: A wireless handset or wireless headset includes a Bluetooth transceiver that is coupleable to an external Bluetooth compatible device, that sends the first audio data to the external Bluetooth compatible device and that receives the second audio data from the external Bluetooth compatible device. The Bluetooth transceiver includes a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a Bluetooth protocol, a processing module that executes the plurality of operational instructions, and a first interface module.

Abstract: The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. The first state machine is configured to select and monitor a first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy inter-face. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.

Abstract: An internal memory uses a resource identifier and an entry point to identify which functional program from an external memory is to be loaded into one of a plurality of overlay spaces established in the internal memory. In executing a program statement, the resource identifier identifies a corresponding functional program to perform a particular functional operation and the identified functional program is then loaded into an overlay space specified by the entry point. The functional program is then executed in the overlay space.

Abstract: A device and a method are disclosed for motion estimation and bandwidth reduction in a memory. The device includes a memory for storing a plurality of frame data, a controller connected to the memory, a first motion estimation processor for performing a coarse-tuning operation and a second motion estimation processor for performing a fine-tuning operation. Similarity between a reference frame and a current frame is calculated based on the averages of every two adjacent pixels in the reference macroblocks and current macroblocks. The amount of calculations for determining motion estimation is greatly reduced, and bandwidth in utilizing the memory is accordingly reduced as motion estimation is advantageously achieved.

Abstract: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory. The system also includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin.

Abstract: A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data.

Abstract: A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

Abstract: A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.

Abstract: The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a data sector of the non-volatile computer memory. The first portion of the redundant memory area includes data associated with the data sector. The first portion of the redundant memory area includes a cyclic redundancy check code.

Abstract: A system and method of determining paper system position and velocity are provided. The method includes receiving a first data triplet at a first time. The first data triplet includes data related to a first coarse digital position, a first channel X analog voltage and a first channel Y analog voltage. The method also includes storing the first time and the first data triplet. The method further includes receiving a second data triplet at a second time. The second data triplet includes data related to a second digital position, a second X analog voltage and a second Y analog voltage. The method also includes evaluating a control loop associated with controlling paper position and velocity. Evaluating the control loop includes determining a velocity of the paper based on the first data triplet, the second data triplet, the first time and the second time.

Abstract: A battery converter, which is used to convert battery voltage to an output voltage to power an integrated circuit in a battery-operated mode, is placed into a battery-charge mode to charge the battery when external power source is present to power the integrated circuit and the battery needs charging.

Abstract: An analog-to-digital converter (ADC) system is disclosed and includes a programmable control register and a plurality of channels, each channel having an associated request bit within the programmable control register. The ADC system also includes a scheduler responsive to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the request bits are set. A method of scheduling analog-to-digital conversion is disclosed and includes receiving a request to schedule an analog-to-digital conversion for a channel of a plurality of channels. The method also includes scheduling an analog-to-digital conversion in response to receiving the request and performing the analog-to-digital conversion based on the request, where data that indicates the request is stored in a programmable control register.

Abstract: A class-D amplifier includes a switching transistor section, a filter, an analog to digital converter, and a feedback module. The switching transistor section is operably coupled to convert a serial input into a switched output signal. The filter is operably coupled to filter the switched output signal to produce an output of the class-D amplifier. The analog to digital converter is operably coupled to convert an analog input into a multi-bit digital signal based on a feedback signal, wherein the serial input corresponds to the multi-bit digital signal. The feedback module is operably coupled to the produce the feedback signal based on at least one varying property of the switching transistor section.

Abstract: The disclosure is directed to a method of determining memory parameters of a memory device. The method includes determining a communication protocol associated with the memory device, determining a page size of the memory device by using the communication protocol to communicate a page of data, determining a block size of the memory device by using the communication protocol to erase a block of the memory device, and determining a capacity of the memory device by using the communication protocol to determine a number of significant address bits.

Abstract: An Infrared (IR) receiver includes a programmable decoder having a normal mode of operation and a proprietary mode of operation. When the programmable decoder is in the normal mode of operation, the programmable decoder decodes frames of an IR data transmission to produce decoded data. When the programmable decoder is in the proprietary mode of operation, the programmable decoder passes data of the IR data transmission during a time out period to produce raw data. The IR receiver also includes a pulse detection circuit that generates a pulse detection signal in response to detecting the IR data transmission. The IR receiver further includes a timer circuit that generates the timeout period in response to the pulse detection signal.

Abstract: An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

Abstract: A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.