Abstract: A method and apparatus for conserving power of a mixed-signal system-on-a-chip having analog circuitry, involving determination of an analog variation parameter that is representative of an integrated circuit fabrication process variance of the integrated circuit, and an operational temperature associated with the analog variation parameter. With the analog variation parameter and the operational temperature, an adjustment signal is determined for a power supply level of the integrated circuit, such that power consumption of the integrated circuit is optimized. Further, in mixed-signal integrated circuits with digital and analog circuitry, a digital variation parameter is determined, where the adjustment signal determination is based on the digital variation parameter and the analog variation parameter with respect to the operational temperature. With such a method and apparatus, power consumption is optimized on an IC-by-IC basis such that power consumption of each IC is optimized.

Abstract: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory. The system also includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mude module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin.

Abstract: A controller includes a volatile random access memory and translation hardware. The volatile random access memory includes a table having at least one entry. The at least one entry includes a portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory. The volatile random access memory is accessible to the translation hardware. The translation hardware is configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and is configured to determine the portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry.

Abstract: A test set for testing a device includes a protocol encoder for formatting a plurality of test data in accordance with a channel protocol to create formatted data. A channel encoder encodes the formatted data in accordance with at least one analog channel parameter and at least one analog perturbation parameter to form a link signal. A first link interface produces a channel signal that is coupled to the device. A second link interface generates a received signal that is based on the channel signal.

Abstract: A real time clock module maintains operating and timing parameters in “non-volatile” or persistent memory when an integrated circuit is powered down. The real time clock module provides is divided into an analog and a digital domain. The analog domain contains a number of persistent registers to store operational parameters and timing parameters. These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator. A clock domain-crossing module operably couples to the persistent registers and allows the analog domain and the digital domain to be synchronized. An input buffer receives the operational and timing parameters for the persistent registers from the digital domain and an output buffer allows the digital domain to retrieve the operational parameters and timing parameters from the persistent registers according to the clock crossing domain module.

Abstract: A audio codec includes a first analog to digital converter for producing a first one-bit data stream, a second one-bit data stream is received from a digital microphone. A selection module produces a one-bit output signal that is the first one-bit data stream when a selection signal is in a first state, and produces a the one-bit output signal that is the second one-bit data stream when the selection signal is in a second state. A decimation and filter module produces a down sampled signal based on the one-bit output signal.

Abstract: A sample rate converter includes an up-conversion module, a linear interpolator module, and a parameter control module. The up-conversion module is operable to convert a first data rate to a second data rate of a data signal. The linear interpolator module is operable to receive the data signal at the second data rate and to produce therefrom a data signal at a desired rate based on at least one parameter. The parameter control module is operable to produce the at least one parameter based on the desired rate.

Abstract: A digital media player. The digital media player includes storage to store media content and a user interface to provide information to a user. The information includes at least one task associated with the media content. The media player also includes a control to allow the user to select at least one task and a processor to perform a task selected by the user.

Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.

Abstract: The disclosure is directed to a portable device including a solid-state memory device and a processor. The solid-state memory device includes a data object including stored data and associated object-based organization data. The solid-state memory device is responsive to the processor. The processor is configured to access the solid-state memory device to retrieve the stored data from the data object and configured to communicate the stored data using a mass storage class (MSC) communication protocol.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.

Abstract: A system and method for detecting a mode of an audio signal is disclosed. The system includes an integrated circuit with an input to receive a signal and an audio processor coupled to the input. The audio processor includes an audio standard detection module, wherein the audio standard detection module detects a characteristic of the received signal that identifies a television audio standard by measuring the energy level of a plurality of different frequency bands of the received signal.

Abstract: Provided is a digitally-controlled linear regulator having noise-shaped component selection. The digitally-controlled linear regulator has a regulated-voltage sensor, a comparator module, a quantization module, and an impedance switching network. The regulated-voltage sensor is operably coupled to sense an output voltage of the digitally-controlled linear regulator to produce a sensed output voltage. The comparator module is operably coupled to compare the sensed output voltage with a reference voltage at a predetermined clock rate to produce a digital regulation signal. The quantization module is operably coupled to quantize the digital regulation signal to produce a quantized regulation signal. The impedance switching network is operably coupled to convert a source voltage into the output voltage of the digitally-controlled linear regulator based on the quantized regulation signal.

Abstract: A method for “booting up” a multiple function device that first involves determining a configuration state of the multiple function device. Based on the configuration state, a functional mode is selected from a number of functional modes. A functional algorithm associated with the selected functional modes is accessed from memory. The functional algorithm is then examined to determine if the algorithm is executable. When the functional algorithm is not executable and the multiple function device is operable coupled to a host, a functional algorithm is downloaded from the host. Otherwise, the device may time-out and is powered down.

Abstract: A successive approximation Analog-to-Digital Converter (“ADC”) having a successive approximation controller operably coupled to convert a control signal into a digital output of the successive approximation ADC, a current-steered Digital-to-Analog Converter operably coupled to convert the digital output of the successive approximation ADC into an analog feedback signal, and a comparator module operably coupled to compare the analog feedback signal with an analog input of the successive approximation ADC to produce the control signal. A further aspect is a method for increasing accuracy for a digital successive approximation of an analog input signal. The method includes determining a signal characteristic of the analog input signal to an Analog-to-Digital Converter (“ADC”), and selecting a reference voltage source of a Digital-to-Analog Converter of the ADC from a plurality of reference voltage sources based on the analog input signal.

Abstract: The disclosure is directed to a controller including a memory interface to a memory device, a device driver configured to access the memory device via the memory interface, and a resource loader to provide a memory location of a resource to the device driver. The device driver is configured to access the memory location on the memory device and to retrieve the resource and an error correction code associated with the resource. Error correction is performed on the resource based on the associated error correction code.

Abstract: A system and method for organizing a non-volatile memory is disclosed. The system includes a non-volatile memory with a first data region and a first redundant memory area associated with the first data region. The first redundant memory area includes a first portion associated with a first data sector. The first portion of the redundant memory area includes a relative sector index and a block number. The redundant memory area also includes a second portion including error correction code (ECC) data.

Abstract: An apparatus and method to synchronize devices in a network to a sub-millisecond timing accuracy. In a first embodiment, the transmission of data is synchronized between a first source device and destination devices communicatively coupled to a network. In a second embodiment, data is deterministically transmitted between a first source device and destination devices communicatively coupled to a network. In a third embodiment, a deterministic network synchronizes the transmission of data between a first source device and destination devices coupled to a network.

Abstract: A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.

Abstract: A phase locked loop circuit is implemented with difference detection module that produces a difference signal based on at least one of phase difference and frequency difference between a reference oscillation and a feedback oscillation. A loop filter module converts the difference signal into a control signal. A controlled oscillation module converts the control signal into an output oscillation. An output oscillation adjust module, coupled to the controlled oscillation module, produces an effective output oscillation based on an oscillation control signal. A divider module converts the effective output oscillation into the feedback oscillation.