Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator controller can include: (i) a first feedback circuit for sensing an output of a switching regulator to compare against a regulation reference, and to generate a control signal suitable for matching the output of the switching regulator to the regulation reference during a steady state operation of the switching regulator; and (ii) a second feedback circuit for sensing a regulation difference between the output and the regulation reference, and to generate an adjustment signal in response to the regulation difference, where the adjustment signal adjusts the control signal under transient conditions to improve transient responses of said switching regulator.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.

Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.

Abstract: Methods and circuits for synchronous rectifier control are disclosed herein. In one embodiment, a synchronous rectifier control circuit can include: (i) a first sense circuit to sense a voltage between first and second power terminals of a synchronous rectifier device prior to a turn-on of the device, where a timing of the turn-on of the synchronous rectifier device is adjustable using a first control signal generated from the first sense circuit; (ii) a second sense circuit configured to sense a voltage between the first and second power terminals after a turn-off of the device, where a timing of the turn-off of the device is adjustable using a second control signal generated from the second sense circuit; and (iii) a driver control circuit configured to receive the first and second control signals, and to generate therefrom a gate control signal configured to drive a control terminal of the synchronous rectifier device.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a power supply can include: (i) an input capacitor coupled to an input terminal that is coupled to a power source, where the power source provides power that is constrained by a predetermined limit; (ii) an output capacitor coupled to an output terminal that is coupled to a load, where the load has a first load condition or a second load condition; (iii) a first regulator to convert an input voltage at the input terminal to an output voltage at the output terminal to power the load; (iv) a second regulator coupled to the first regulator; and (v) an energy storage element coupled to the second regulator, where the second regulator delivers energy from the energy storage element to the first regulator to maintain regulation of an output voltage at the output terminal when in the second load condition.

Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

Abstract: Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a power supply can include: (i) an input capacitor coupled to an input terminal that is coupled to a power source, where the power source provides power that is constrained by a predetermined limit; (ii) an output capacitor coupled to an output terminal that is coupled to a load, where the load has a first load condition or a second load condition; (iii) a first regulator to convert an input voltage at the input terminal to an output voltage at the output terminal to power the load; (iv) a second regulator coupled to the first regulator; and (v) an energy storage element coupled to the second regulator, where the second regulator delivers energy from the energy storage element to the first regulator to maintain regulation of an output voltage at the output terminal when in the second load condition.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a power supply can include: (i) an input capacitor coupled to an input terminal that is coupled to a power source, where the power source provides power that is constrained by a predetermined limit; (ii) an output capacitor coupled to an output terminal that is coupled to a load, where the load has a first load condition or a second load condition; (iii) a first regulator to convert an input voltage at the input terminal to an output voltage at the output terminal to power the load; (iv) a second regulator coupled to the first regulator; and (v) an energy storage element coupled to the second regulator, where the second regulator delivers energy from the energy storage element to the first regulator to maintain regulation of an output voltage at the output terminal when in the second load condition.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; after the doped body region formation, forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; after the doped body region formation, forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.

Abstract: Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.