Abstract: The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected systems, multiple bank/access block/sector/sub-array with random data throughput can also be realized. A memory including a plurality of independently accessible memory banks, a READ BUS for selectively reading to a selected on of the memory banks, and a WRITE BUS independent of the READ BUS for selectively writing to a selected one of the memory banks, is described.

Abstract: A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.

Abstract: A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.

Abstract: A memory 200 includes a first memory segment 302 comprising an array of rows and columns of memory cells, a selected column of cells in the first segment 302 accessed through a dedicated sense amplifier 304 associated with the first segment. A second memory segment 302 comprises an array of rows and columns of memory cells, a selected column of cells in the second memory segment 302 accessed through a dedicated sense amplifier 304 associated with the second segment. A Read Input/Output line 306a is coupled to the sense amplifier accessing the selected column of the first segment 302 for reading data from the first segment during a selected access cycle. A Write Input/Output line 306b is coupled to the sense amplifier 304 accessing the selected column of the second segment 302 for simultaneously writing data to the second memory segment 302 during the selected access cycle.

Abstract: A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.

Abstract: Memory 200 having an array of rows and columns of memory cells, each column associated with a pair of complementary bitlines 302a, 302b. An access sense amplifier 203 coupled to each pair of complementary bitlines 302a, 302b for sensing and latching data from cells along a selected row during a first portion of a random access cycle. Refresh sense amplifier 204 is coupled to each pair of complementary bitlines for 302a, 302b for refreshing data from cells along a selected row during a second portion of the random access cycle.

Abstract: A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.

Abstract: Memory 900 includes an array 401 of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port (PORT1) is utilized for accessing selected ones of the memory cells using the first wordline and the first bitline of corresponding ones of the rows and columns, first port (PORT1) associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses via first processing device 101 using a time base and an access-type required by such first processing device. A second port (PORT2) is utilized for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, second port (PORT2) associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device 1002.

Abstract: A memory 700 having an array 701 of rows and columns of dynamic memory cells 301, cells 301 of each row coupled to a refresh wordline 303a and an access wordline 303b and cells 301 of each column coupled to a refresh bitline 302a and an access bitline 302b. Refresh circuitry 711, 712, refreshes selected rows of cells corresponding to a refresh wordline 303a and a corresponding one refresh bitline 302a. Access circuitry accesses selected cells of a selected row using corresponding access wordline 303b and corresponding one of the access bitlines 302b. The access circuitry includes a new address detector of 709 for detecting receipt of a new address of said memory, a row decoder 702 for selecting access wordline in response to receipt of the new address and access sense amplifiers 703 and an access column decoder 704 accesses at least one cell along the selected wordline 303b using the corresponding access bitline 302b.

Abstract: A dynamic random access memory 400 includes an array 401 of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines 603 and first and second bitlines 602. A direct input/output data path 402 having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.

Abstract: A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: A method of permanently programming selected cells of dynamic random access memory cell array. First selected cell is programmed to a Logic 1 by grounding a first capacitor plate of the first cell, and applying a programming voltage to a second capacitor plate common to the cells of the array. A dielectric disposed between the first capacitor plate and the second capacitor plate breaks down, thereby shorting the first and second capacitor plates. A second selected cell is programmed to store a Logic 1 by allowing a first capacitor of the second cell to float during a period when the programming voltage is applied to the second capacitor plate.

Abstract: Multivalued memory cell 300 includes a latch 300 having a latching node operating between a variable voltage rail and a fixed voltage rail. Circuitry 303 allows for latching of node to a voltage level of the variable voltage rail, the voltage level at the latched node representing a data value. Circuitry 303 provides for the outputing of the voltage level from the latched node.

Abstract: A memory 400 including a memory cell 501 disposed at the intersection of an addressable row and addressable column, memory cell 501 being accessible via a selected one of a pair of wordlines 503a, 503b associated with the row and a selected one of a pair of bitlines 502a, 502b associated with the column.

Abstract: A memory 200 including an array 201 of rows and columns of 2-transistor, 1-capacitor memory cells 301 of the cells of each row coupled to first and second wordlines 303a, 303b and the cells of each column coupled to a pair of bitlines 302a, 302b. Refresh circuitry 208 activates the first wordline 303a plus selected said row and refreshes the cells 301 of that row through a first one of the bitlines 302a of each of the columns. Data access circuitry 202, 204 substantially simultaneously activates the second said wordline 303b of a second selected row and accesses selected cells of the second row through a second one of the bitlines 302b in the corresponding columns.

Abstract: Memory 400 is fabricated as a single integrated circuit chip and includes an array 402 of memory cells and circuitry 404/405/413 for accessing selected memory cells in array 402. At least one local ALU 414 is included for receiving data accessed from selected cells of array 402 and performing a selected operation thereon.

Abstract: A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.