Abstract: A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.

Abstract: A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location.

Abstract: A memory 400 comprises a plurality of banks 401 and global access control circuitry 406. Each of the plurality of banks includes first and second arrays 506, 402 of memory cells, first accessing circuitry 413, 507 for selectively accessing cells in the first array in response to address bits, and second accessing circuitry 404, 413 for selectively accessing cells in the second array in response to address bits. Storage circuitry 502 within each bank 401 stores previously received address bits. Circuitry for comparing 503 within each bank compares received address bits with stored address bits in storage circuitry 503, with first accessing circuitry 413, 507 accessing cells in first array 506 addressed by the stored address bits when stored address bits and received address bits match and second accessing circuitry 404, 413 accessing cells in second array 402 addressed by the received address bits when the stored address bits and the received address bits differ.