Abstract: The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n? epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p+ contact diffusion region and the n+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.

Abstract: The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N? epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p? diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.

Abstract: A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be easily scaled down to obtain a high-density trench DMOS power transistor with ultra low on-resistance, low gate-interconnection parasitic resistance, and high device ruggedness.

Abstract: A self-aligned source structure is disclosed by the present invention, in which a p-body diffusion region is formed in an n? epitaxial silicon layer on an n+ silicon substrate through a patterned window; a p+ diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sidewall dielectric spacer being formed over and on a silicon nitride layer; an n+ source diffusion ring is formed in a surface portion of the p-body diffusion region and on an extended portion of the p+ diffusion region through a second self-aligned implantation window formed between the silicon nitride layer and a masking layer surrounded by the first sidewall dielectric spacer; and a self-aligned source contact window is formed on the n+ source diffusion ring surrounded by a second sidewall dielectric spacer and on the p+ diffusion region surrounded by the n+ source diffusion ring.

Abstract: A self-aligned planar DMOS transistor structure is disclosed, in which a p-body diffusion region is selectively formed in an n?/n+ epitaxial silicon substrate; a self-aligned p+ contact diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sacrificial dielectric spacer; a self-aligned n+ source diffusion ring is formed in a surface portion of the p-body diffusion region through a second self-aligned implantation window formed between a protection dielectric layer and a self-aligned implantation masking layer surrounded by the sacrificial dielectric spacer; a self-aligned source contact window is formed on the self-aligned n+ source diffusion ring surrounded by a sidewall dielectric spacer and on the self-aligned p+ contact diffusion region surrounded by the self-aligned n+ source diffusion ring; and a heavily-doped polycrystalline-silicon gate layer is selectively silicided in a self-aligned manner.

Abstract: A stack-gate flash cell structure of the present invention comprises a gate region being formed between common-source/drain regions. The common-source/drain region comprises a common-source/drain diffusion region, an etched-back planarized silicon dioxide layer being formed over a portion of a tunneling dielectric layer, and a pair of extended floating-gate spacers being formed over side portions of the etched-back planarized silicon dioxide layer. The gate region comprises a major floating-gate being integrated with nearby two extended floating-gate spacers to form an integrated floating-gate. A word line together with an intergate dielectric layer being at least formed over the integrated floating-gate are simultaneously patterned and etched. A cell isolation region is formed outside of the word line and between the common-source/drain regions. The stack-gate flash cell structure is used to implement two contactless flash memory arrays.

Abstract: A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.

Abstract: A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating-gates. The common-source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions being divided by a shallow trench isolation formed between a pair of first sidewall dielectric spacers. A word line being formed over an intergate dielectric layer is at least formed over the pair of floating-gates and the select-gate dielectric layer. Based on common-source/drain diffusion regions and isolated source/drain diffusion regions of the dual-bit floating-gate cell structure, two different contactless flash memory arrays are formed.

Abstract: A self-aligned split-gate flash cell structure of the present invention comprises a ridge-shaped floating-gate layer being formed on a first gate dielectric layer with a first intergate dielectric layer being formed on its top portion and a second intergate dielectric layer being formed on its inner sidewall; a control/select-gate conductive layer being formed at least over a second gate dielectric layer and the first/second intergate dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the control/select-gate conductive layer. The self-aligned split-gate flash cell structure is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

Abstract: A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.

Abstract: Methods of fabricating a stack-gate flash memory array are disclosed by the present invention, in which a self-aligned integrated floating-gate layer includes a major floating-gate layer formed on a thin tunneling dielectric layer and two extended floating-gate layers formed on planarized filed-oxides (FOX); a high-conductivity word line is formed by a composite conductive layer of metal or silicide/barrier-metal/doped polycrystalline- or amorphous-silicon as a control-gate layer and is encapsulated by the dielectric layers; a self-registered common-source/drain bus line is formed on a flat bed formed by common-source/drain diffusion regions and planarized field-oxides; a self-registered common-source/drain landing island is formed on a common-source/drain diffusion region to act as a self-aligned contact and a dopant diffusion source for forming a shallow heavily-doped commmon-source/drain diffusion region.

Abstract: A self-aligned split-gate flash memory cell and its contactless memory array in which a floating-gate length and a control-gate length of a self-aligned split-gate flash memory cell are separately defined by two sidewall dielectric spacers being formed over the same sidewall on a common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array includes a plurality of common-source/drain conductive bus lines being formed alternately over the first/second flat beds; and a plurality of word lines together with the control-gates of a plurality of self-aligned split-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.

Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: A self-aligned split-gate flash memory cell and its contactless memory array are disclosed by the present invention, in which a floating-gate length and a control-gate length of a self-aligned split-gate flash memory cell are separately defined by two sidewall dielectric spacers being formed over the same sidewall on a common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array comprises a plurality of common-source/drain conductive bus lines being formed alternately over the first/second flat beds; and a plurality of word lines together with the control-gates of a plurality of self-aligned split-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices; the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using a shallow-trench-isolation (STI) structure so that the applied control-gate voltage for programming and erase can be reduced; the third spacer technique is used to define the gate length of a scalable stacked-gate structure; and the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.

Abstract: A self-aligned split-gate flash memory cell and its contactless NOR-type memory array are disclosed by the present invention, which comprise a shallow-trench-isolation structure having an integrated floating-gate structure and the embedded double-sides erase cathodes; a self-aligned split-gate flash memory cell having a steep or one-side tapered floating-gate structure; a bit line integrated with planarized common-drain conductive islands; and a common-source conductive bus line. Therefore, the present invention offers a smaller cell area, a higher coupling ratio through an integrated floating-gate structure, a higher erasing speed through the embedded double-sides erase cathodes, higher contact integrity for shallow junction through a common-drain conductive island, and lower bus-line resistance and capacitance through a common-source conductive bus line.

Abstract: A scalable split-gate flash memory cell structure of the present invention comprises a common-source region, a scalable split-gate region being formed by a sidewall dielectric spacer, and a scalable common-drain region, wherein the scalable split-gate region comprising a floating-gate region being defined by another sidewall dielectric spacer has a tip-cathode line for erasing. The cell size of the present invention is scalable and can be made to be equal to 4F2 or smaller. The scalable split-gate flash memory cell structure is used to implement two contactless flash memory arrays: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array for high speed read/write/erase operations. Moreover, the contactless flash memory arrays can be fabricated with less critical masking steps as compared to the prior art.

Abstract: A self-aligned split-gate flash memory cell of the present invention comprises an integrated floating-gate layer being at least formed on a first gate-dielectric layer having a first intergate-dielectric layer formed on its top and a second intergate-dielectric layer formed on its inner sidewall; a planarized control/select-gate layer being at least formed on a second gate-dielectric layer and the first second intergate-dielectric layers; a common-source and a common-drain diffusion regions; and an integrated source-side erase structure being at least formed on a portion of the common-source diffusion region and on a tunneling-dielectric layer formed over an outer sidewall of the integrated floating-gate layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type array and a contactless parallel common-source/drain conductive bit-lines array.

Abstract: A self-aligned split-gate flash memory cell of the present invention comprises a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer and another portion formed at least on a single-side tip-shaped floating-gate structure being formed on a first gate-dielectric layer, wherein a dielectric layer is formed over the single-side tip-shaped floating-gate structure to act as a first intergate-dielectric layer and a second intergate-dielectric layer is formed over an inner sidewall of the single-side tip-shaped floating-gate structure. The self-aligned split-gate flash memory cell is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.