Abstract: A scaled stack-gate non-volatile semiconductor memory device having atapered floating-gate structure is disclosed by the present invention, in which a stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized. A deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region are formed as the first embodiment of the present invention. The deeper double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the second embodiment of the present invention. The shallower double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the third embodiment of the present invention.

Abstract: A stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized to form a first dielectric layer over the sidewalls of the control-gate layer, a second dielectric layer over the sidewalls of the floating-gate layer, and a thicker oxide layer over each side portion of the active region having a gradedoxide layer formed near two gate edges. An integrated source/drain landing island having a portion formed over a source/drain diffusion region for contact and an extended portion formed over a second dielectric layer and on a graded-oxide layer is acted as a field-emission cathode/anode. The scaled stack-gate flash memory device of the present invention can be programmed and erased through two-tunneling paths or one tunneling path without involving the channel region.

Abstract: A scalable dual-bit flash memory cell of the present invention comprises a scalable gate region having a pair of floating-gate structures with a select-gate region being formed therebetween and a planarized control/select-gate over a second gate-dielectric layer being formed over the pair of floating-gate structures with or without a pair of second sidewall dielectric spacers being formed over a pair of floating gates; a conductive bit line together with a first sidewall dielectric spacer being formed over a flat bed formed by a source/drain diffusion region and etched raised field-oxide layers. A contactless dual-bit flash memory array of the present invention comprises a plurality of conductive bit-lines being formed transversely to a plurality of parallel STI regions and a plurality of word lines integrated with a plurality of control-gate/select-gates of the described cells being patterned and formed transversely to the plurality of conductive bit-lines.

Abstract: The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the present invention, in which the first conductive gate layer is etched to form a steep-gate structure or a taper-gate structure. The metal layer is encapsulated by a second masking dielectric layer formed on the top and a first dielectric spacer formed on both sides, no interaction would occur between the metal layer and the first conductive gate layer, a highly-conductive nature of the metal layer for gate interconnection can be preserved. A thick silicide layer is formed by a two-step self-aligned silicidation process and a conductive barrier-metal layer is formed to eliminate the interaction between the thick silicide layer and the first conductive gate layer, a highly conductive nature of the thick silicide layer for gate interconnection can be obtained.

Abstract: A high-density, high-speed, low-power, scalable split-gate memory device and its fabrication are disclosed. The channel length of a control-gate device and the channel length of a floating-gate device in a split-gate flash memory device can be tailored separately to have a dimension much smaller than the minimum feature size of technology used. A sidewall erase cathode using a thin polycrystalline-silicon layer as the floating gate may be implemented. The sidewall erase cathode may be implemented on two advanced high-density isolation structures having embedded double-sides erase cathodes and high coupling ratio to form triple-sides erase cathodes, which provide high-efficiency, self-limiting erasing from the floating gate to the control gate. Moreover, self-aligned silicidation is applied to the control gate, the source/common buried source, and the drain of the device to reduce contact and interconnect resistances.

Abstract: Non-volatile semiconductor memory device for high-density and high-speed mass storage applications is described, in which a method for simultaneously fabricating field-oxide isolation and floating gate of non-volatile semiconductor memory device having high coupling ratio and embedded double-sides erase cathodes and a method for fabricating scalable split-gate non-volatile semiconductor memory device are disclosed. The field-oxide isolation is obtained by a special multilayer oxidation masking structure of the present invention, in which the field-doping encroachment and the bird's beak extension into the active regions of the minimum feature size can be eliminated and the smaller isolation area occupied together with the embedded double-sides erase cathodes are prepared for fabricating scalable split-gate non-volatile semiconductor memory device of the present invention.