Abstract: A high performance computing system includes one or more blade enclosures having a cooling manifold and configured to hold a plurality of computing blades, and a plurality of computing blades in each blade enclosure with at least one computing blade including two computing boards. The system further includes two or more cooling plates with each cooling plate between two corresponding computing boards within the computing blade, and a fluid connection coupled to the cooling plate(s) and in fluid communication with the fluid cooling manifold.

Abstract: Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor's native hardware addressing capabilities. The invention also enables computer system transactional capabilities to scale well beyond the transactional capabilities of those found computer systems today.

Abstract: An algorithm for mapping memory and a method for using a high performance computing (“HPC”) system are disclosed. The algorithm takes into account the number of physical nodes in the HPC system, and the amount of memory in each node. Some of the nodes in the HPC system also include input/output (“I/O”) devices like graphics cards and non-volatile storage interfaces that have on-board memory; the algorithm also accounts for the number of such nodes and the amount of I/O memory they each contain. The algorithm maximizes certain parameters in priority order, including the number of mapped nodes, the number of mapped I/O nodes, the amount of mapped I/O memory, and the total amount of mapped memory.

Abstract: The present invention relates to a temporal base method of mutual exclusion control of a shared resource. The invention will usually be implemented by a plurality of host computers sharing a shared resource where each host computer will read a reservation memory that is associated with the shared resource. Typically a first host computer will perform and initial read of the reservation memory and when the reservation memory indicates that the shared resource is available, the first host computer will write to the reservation memory. After a time delay, the host computer will read the reservation memory again to determine whether it has won access to the resource. The first host computer may determine that it has won access to the shared resource by checking that data in the reservation memory includes an identifier corresponding to the first host computer.

Abstract: Tape device paths, library slots and drive information are automatically collected by agents at nodes in a library cluster. The information is reported to a central server database. The central server accesses the information and maps tape devices to path information so an administrator may easily have access to configuration information for the tape device cluster. When a tape device cluster is updated, for example through changes to a device, an added device, device failure or some other reason, the change is detected and the cluster configuration is automatically updated.

Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Abstract: A high performance computing system includes one or more blade enclosures configured to hold a plurality of computing blades, a connection interface, coupled to the one or more blade enclosures, having one or more connectors and a shared power bus that distributes power to the one or more blade enclosures, and at least one power shelf removably coupled to the one or more connectors and configured to hold one or more power supplies. The system may further include the computing blades and the power supplies. The power shelf may include a power distribution board configured to connect the power supplies together on the shared power bus.

Abstract: In an embodiment, a micro ethernet connector includes an outer housing that has a recessed front end and a back end. The micro ethernet connector further includes an inner housing that is disposed within the recessed front end of the outer housing. The inner housing has an exposed end. The exposed end includes a recessed channel. The volume of the recessed channel is substantially equal to the volume of a correspondingly shaped protruding printed circuit board of a male micro ethernet connector. A plurality of spring-biased connectors are disposed within the recessed channel of the inner housing.

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract: A system and method for remote rendering of computer graphics wherein user transactions are reliable and the transmission of rendered graphics is relatively fast. The invention is implemented in a client server context, where a computer graphics application and rendering resources are located at a server. A user controls the graphics application through a client machine connected to the server through a computer network. The user's commands are sent from the client to the server, while rendered computer graphics are transmitted from the server to a display at the client. Different transport protocols are used, depending on the requirements of a particular transmission. Data related to user interactions is transmitted using a relatively reliable transport protocol, such as TCP. Rendered subject graphics data is transmitted from the server to the client using a less reliable but faster transport protocol, such UDP.

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract: A center of rotation may automatically be selected for graphically displayed data. The rotation center may be automatically selected based on what is determined to be of interest to the user, the current display of the data, and other parameters. For example, if a user has selected a portion of data, the center of rotation may be within the center of the selected data. If a user has positioned a cursor within a portion of displayed data, the center of rotation may be the center of the data portion including the cursor. If the data as a whole is approximately centered about the graphical coordinate origin, or within a threshold of the origin, the data may be rotated about the origin. If the data as a whole is approximately centered at least a certain distance away from the graphical coordinate origin, the data may be rotated about the center of the data as a whole.

Abstract: A data visualization system with the capability of viewing large amounts of data in a parallel coordinates system. Large amounts of data are displayed in parallel coordinates by grouping together data points by bins and representing grouped data with fewer graphical elements. The fewer graphical elements simplify the graphical representation of the data while still providing information about the density or volume of data occupying a particular space. Bins are determined for each axis. The volume of connections between a pair of neighboring pair of bins may be represented by modifying an aspect of the connection based on the volume.

Abstract: A computer system has a liquid cooling system with a main portion, a cold plate, and a closed fluid line extending between the main portion and the cold plate. The cold plate has an internal liquid chamber fluidly connected to the closed fluid line. The computer system also has a hot swappable computing module that is removably connectable with the cold plate. The cold plate and computing module are configured to maintain the closed fluid line between the main portion and the cold plate when the computing module is being connected to or removed from the cold plate.

Abstract: A computer system with read/write access to storage devices creates a snapshot of a data volume at a point in time while continuing to accept access requests to the mirrored data volume by copying before making changes to the base data volume. Multiple snapshots may be made of the same data volume at different points in time. Only data that is not stored in a previous snapshot volume or in the base data volume are stored in the most recent snapshot volume.

Abstract: Embodiments of the present invention perform a method for reading data from, writing data to, powering on, or configuring a block device without the kernel translating a file system operation into a block device operation. This is implemented by a using a core module to couple applications running in user space to a character device through a character device driver, the core module configures the character device to communicate with a block device through a block device driver without the kernel translating a file system command into a block device command.

Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).

Abstract: A data visualization technique is provided with the capability of manipulating bins of data through an interactive graphical presentation of displayed data. When a histogram is generated from stored data, a user may interact directly with the histogram columns to change columns position, width and height. A user, for example, may click and drag a particular side of a bin to change the lower or upper limit of the bin, click and drag the top of a bin to change the size/height of the bin (i.e., number of data points/elements within the bin), or click and drag the center of the bin to move or reposition the bin. The techniques may be applied to other graphical representations of data as well, such as splat graphical displays of data.

Abstract: Data visualization that interactively rotates data about a particular axis or translates data in a particular plane based on input received outside the axis space. Data to be visualized is accessed by a data visualization application. The data may be structured or unstructured, filtered and analyzed. The accessed data may be displayed through an interface of the visualization application for a user. The coordinate system for displaying the data may also be displayed. A user may rotate data about a particular axis of the coordinate system or translate data in a particular plane by providing a continuous input within a graphics portion of an interface. The input may be associated with a virtual track ball.