Patents Assigned to Silicon Graphics International Corp.
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Publication number: 20140281214Abstract: Quotas are tracked for user usage of hard disk drive space and offline backup storage space. The quota is enforced against the total space utilized by a user, not just high tier hard drive space usage. When data is migrated from hard disk drive space to backup storage space, data metadata is updated to reflect data kept offline for the user. As such, when users request to store new data, the data usage of hard disk space and backup storage space is determined from the metadata that reflects both data types, and the total storage spaced for the user is used to grant or reject the user's request to store more data in the system.Type: ApplicationFiled: May 17, 2013Publication date: September 18, 2014Applicant: Silicon Graphics International Corp.Inventors: Kevan Flint Rehm, Benjamin Paul Myers
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Publication number: 20140281322Abstract: Embodiments of the invention includes identifying the priority of data sets based on how frequently they are accessed by data center compute resources or by other measures assigning latency metrics to data storage resources accessible by the data center, moving data sets with the highest priority metrics to data storage resources with the fastest latency metrics, and moving data sets with lower priority metrics to slower data storage resources with slower latency metrics. The invention also may be compatible with or enable new forms of related applications and methods for managing the data center.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Silicon Graphics International Corp.Inventor: Charles Robert Martin
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Publication number: 20140281266Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Silicon Graphics International Corp.Inventor: Brian J. Johnson
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Patent number: 8838658Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.Type: GrantFiled: March 11, 2013Date of Patent: September 16, 2014Assignee: Silicon Graphics International Corp.Inventors: Daniel Moore, Andrew Gilfind
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Publication number: 20140258679Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Silicon Graphics International Corp.Inventor: Thomas Edward McGee
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Publication number: 20140250252Abstract: A modular first-in first-out circuit including at least three non-addressable memory blocks forming a data pipeline is disclosed. At least two of the memory block including a data storage structure for receiving as input data from a global data bus and a control logic structure including logic for determining whether data should be added to the data storage structure from the global data bus and whether any data within the data storage structure should be transferred to the output of the memory block. The data storage structure of the at least two memory blocks includes a first data input for selectively receiving data from the global data bus and a second data input for selectively receiving data from a previous memory block in the modular first-in first-out circuit.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: SILICON GRAPHICS INTERNATIONAL CORP.Inventor: Eric C. Fromm
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Publication number: 20140245079Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: SILICON GRAPHICS INTERNATIONAL CORP.Inventor: Silicon Graphics International Corp.
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Patent number: 8812765Abstract: A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.Type: GrantFiled: March 21, 2013Date of Patent: August 19, 2014Assignee: Silicon Graphics International Corp.Inventors: Donglai Dai, Randal Passint
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Patent number: 8812721Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: December 4, 2012Date of Patent: August 19, 2014Assignee: Silicon Graphics International Corp.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20140188955Abstract: A computer system with read/write access to storage devices creates a snapshot of a data volume at a point in time while continuing to accept access requests to the mirrored data volume by copying before making changes to the base data volume. Multiple snapshots may be made of the same data volume at different points in time. Only data that is not stored in a previous snapshot volume or in the base data volume are stored in the most recent snapshot volume.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Applicant: Silicon Graphics International Corp.Inventor: Kenneth S. Beck
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Patent number: 8760456Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing.Type: GrantFiled: September 30, 2013Date of Patent: June 24, 2014Assignee: Silicon Graphics International Corp.Inventor: Phillip C. Keslin
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Publication number: 20140126143Abstract: A high performance computing system includes one or more blade enclosures configured to hold a plurality of computing blades, a connection interface, coupled to the one or more blade enclosures, having one or more connectors and a shared power bus that distributes power to the one or more blade enclosures, and at least one power shelf removably coupled to the one or more connectors and configured to hold one or more power supplies. The system may further include the computing blades and the power supplies. The power shelf may include a power distribution board configured to connect the power supplies together on the shared power bus.Type: ApplicationFiled: July 24, 2013Publication date: May 8, 2014Applicant: Silicon Graphics International Corp.Inventors: Steven J. Dean, Robert E. Mascia, Harvey J. Lunsman, Michael Kubisiak, David R. Collins, Timothy S. McCann
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Publication number: 20140126141Abstract: A high performance computing system includes one or more blade enclosures having a cooling manifold and configured to hold a plurality of computing blades, and a plurality of computing blades in each blade enclosure with at least one computing blade including two computing boards. The system further includes two or more cooling plates with each cooling plate between two corresponding computing boards within the computing blade, and a fluid connection coupled to the cooling plate(s) and in fluid communication with the fluid cooling manifold.Type: ApplicationFiled: June 28, 2013Publication date: May 8, 2014Applicant: Silicon Graphics International Corp.Inventors: Steven J. Dean, Richard B. Salmonson, Russell E. Stacy, Roger Ramseier, Mark Maloney
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Patent number: 8713576Abstract: Techniques for balancing processing loads when performing parallel tasks on one or more processing nodes that share memory resources are provided. For some embodiments, the techniques involve distributing work according to an alternate block cyclic distribution scheme of at least one dimension, wherein work processes are assigned to sets of threads in at least first and second adjacent blocks based on round-robin manner according to a first sequence and an alternate round-robin manner according to a second sequence that is a mirror image of the first sequence, respectively.Type: GrantFiled: February 21, 2007Date of Patent: April 29, 2014Assignee: Silicon Graphics International Corp.Inventor: Jean-Pierre Panziera
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Publication number: 20140108736Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: Silicon Graphics International, Corp.Inventor: Jeffrey S. Kuskin
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Publication number: 20140108458Abstract: Resource acquisition requests for a filesystem are executed under user configurable metering. Initially, a system administrator sets a ratio of N:M for executing N read requests for M write requests. As resource acquisition requests are received by a filesystem server, the resource acquisition requests are sorted into queues, e.g., where read and write requests have at least one queue for each type, plus a separate queue for metadata requests as they are executed ahead of any waiting read or write request. The filesystem server controls execution of the filesystem resource acquisition requests to maintain the ratio set by the system administrator.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: Silicon Graphics International, Corp.Inventors: David Chinner, Michael Anthony Gigante
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Patent number: 8683021Abstract: A computer system with read/write access to storage devices creates a snapshot of a data volume at a point in time while continuing to accept access requests to the mirrored data volume by copying before making changes to the base data volume. Multiple snapshots may be made of the same data volume at different points in time. Only data that is not stored in a previous snapshot volume or in the base data volume are stored in the most recent snapshot volume.Type: GrantFiled: August 16, 2011Date of Patent: March 25, 2014Assignee: Silicon Graphics International, Corp.Inventor: Kenneth S. Beck
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Publication number: 20140068201Abstract: Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor's native hardware addressing capabilities. The invention also enables computer system transactional capabilities to scale well beyond the transactional capabilities of those found computer systems today.Type: ApplicationFiled: August 28, 2013Publication date: March 6, 2014Applicant: Silicon Graphics International Corp.Inventor: Eric Fromm
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Publication number: 20140068627Abstract: Embodiments of the invention relate to a system and method for dynamically scheduling resources using policies to self-optimize resource workloads in a data center. The object of the invention is to allocate resources in the data center dynamically corresponding to a set of policies that are configured by an administrator. Operational parametrics that correlate to the cost of ownership of the data center are monitored and compared to the set of policies configured by the administrator. When the operational parametrics approach or exceed levels that correspond to the set of policies, workloads in the data center are adjusted with the goal of minimizing the cost of ownership of the data center. Such parametrics include yet are not limited to those that relate to resiliency, power balancing, power consumption, power management, error rate, maintenance, and performance.Type: ApplicationFiled: June 29, 2013Publication date: March 6, 2014Applicant: Silicon Graphics International Corp.Inventors: Eng Lim Goh, Christian Tanasescu, George L. Thomas, CHarlton Port
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Publication number: 20140032766Abstract: A cluster of computing systems is provided with guaranteed real-time access to data storage in a storage area network. Processes issue request for bandwidth reservation which are initially handled by a daemon on the same node as the requesting processes. The local daemon determines whether bandwidth is available and, if so, reserves the bandwidth in common hardware on the local node, then forwards requests for shared resources to a master daemon for the cluster. The master daemon makes similar determinations and reservations for resources shared by the cluster, including data storage elements in the storage area network and grants admission to the requests that don't exceed total available bandwidth.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: Silicon Graphics International Corp.Inventor: Michael A. Raymond