Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract: A system for receiving and decrypting media content encrypted according to the HDCP protocol is described herein. A receiving device coupled to a plurality of content channels includes an authentication engine to authenticate each content channel and to generate an initial session key associated with each authenticated content channel. The content channels can be, for example, an HDMI channel or an MHL3 channel. A session key indicator indicating a session key used to encrypt media content is received, and an updated session key is generated. The receiving device also includes a stream cipher engine configured to decrypt received encrypted media content using the updated session key. Decrypted media content can then be displayed, for instance on a display of the receiving device.

Abstract: A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

Abstract: A system for detecting and mitigating bit errors in transmitted media is described herein. A source device encodes a frame of video, and generates an error code representative of a portion of the encoded frame of video. The portion of encoded frame and the error code are provided to a sink device via a communication channel, such as an HDMI or MHL3 channel. A second error code is generated by the sink device based on the portion of encoded frame, and the error code and second error code are compared to determine if the portion of encoded frame includes an error. If no error is detected, the portion of encoded frame is decoded and outputted. If an error is detected, the portion is replaced with frame data based on at least one other portion of encoded frame to produce a mitigated frame, and the mitigated frame is outputted.

Abstract: A transmitter and receiver for communication of multimedia streams across a multi-lane communications link. The transmitter packetizes multimedia streams according to a link layer protocol and distributes the packets across multiple lanes of a communications link. The entire packet, including the header and payload, can be distributed across the lanes in an ordered sequence to increase utilization of the communication lanes. The transmitter may also packetize multiple multimedia streams and intermix the packets across the lanes of the communication lane. The receiver extracts the packets that are distributed across the multiple lanes and decodes the packets into the multimedia streams.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: A mechanism for facilitating dynamic counter synchronization and packetization for data streams being communicated over communication devices is described. In one embodiment, a method includes detecting an audio/video (A/V) data stream being encrypted and/or decrypted using one or more high-bandwidth digital content protection (HDCP) engines, where the A/V data stream is communicated between a source device and a sink device. The method may further include dividing a video stream portion of the A/V data stream into a plurality of frames if the A/V data stream relates to a high-definition multimedia interface (HDMI), and synchronizing counter values with indicators within the plurality of frames.

Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.

Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.

Abstract: Embodiments of the invention are generally directed to transmission of multiple protocol data elements via an interface utilizing a data tunnel over a control channel. An embodiment of an apparatus includes a transmitter or receiver for the transmission or reception of data; a processing element for handling the data of the apparatus; and a connector for the transfer of the data, the connector to connect to a data channel and to connect to a control channel. The processing element is to provide for transfer of data of a first protocol in the control channel, the transfer of data via the control channel including the use of one or more generic commands of the first protocol for the transfer of data of a second protocol. Data of the second protocol is optimized before the data of the second protocol is sent over the first protocol, and the data transfer in the data channel and data transfer in the control channel are simultaneous at least in part.

Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

Abstract: Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

Abstract: Techniques and mechanisms for formatting digital audio-video (“AV”) information. In an embodiment, interface logic includes circuitry to receive digital AV information which, in one or more respects, is according to or otherwise compatible with a first interface specification. The interface logic changes a format of the digital AV information to allow for subsequent physical layer processing which is according to a second interface specification. In another embodiment, conversion logic receives analog signals according to the second interface specification and, based on such analog signals, performs digital information processing for subsequent generation of other analog signals to be transmitted according to the first interface specification.

Abstract: A media access controller (MAC) generates a composite packet having an optimized format for carrying audio, video, and data traffic. A header portion of the composite packet is encoded separately from a data portion of the composite packet. A physical device interface (PHY) is coupled to the MAC. The PHY encodes and decodes between a digital signal and a modulated analog signal. The PHY comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). A radio frequency (RF) transmitter is coupled to the PHY to transmit data.

Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Abstract: A port multiplier dynamically determines and reports its identity based on a number of supported downstream port connections. The number of supported downstream port connections can dynamically change. The port multiplier identifies devices connected to its downstream ports, whether storage devices or other port multipliers. Based on a total number of downstream ports, the port multiplier reports its identity upstream. The upstream reporting can be to another port multiplier, or the host device if directly connected to the host device. The port multiplier receives storage address space allocation from upstream based on its reported identity, and allocates the storage address space to its downstream ports.

Abstract: A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Abstract: Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.

Abstract: The disclosed embodiments relate to a retro-directive array that facilitates a tracking operation. This retro-directive array includes a first antenna configured to receive an input signal which is substantially circularly polarized from a tracking device. The first antenna separates the input signal into two signal components (e.g., Ex and Ey) associated with different orthogonal polarizations, wherein the two signal components comprise a quadrature signal wherein Ey=j·Ex. The retro-directive array also includes a bi-directional quadrature gain (BQG) module coupled to the first antenna which is configured to boost the quadrature signal. It additionally includes a second antenna which configured to transmit the boosted quadrature signal to the tracking device.

Abstract: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.