Abstract: Described herein are an apparatus, system, and method having a compact symmetrical transition structure for RF applications. The apparatus comprises: first and second ground planes each of which having respective truncated edges, the first and second ground planes being parallel to one another and separated by a multi-layer substrate; a strip line positioned between the first and second ground planes; and a symmetrical transition structure, coupled to the strip line and the first and second ground planes near their respective truncated edges, and further coupled to a broadside coupled line (BCL).

Abstract: Embodiments of the invention are generally directed to identification and handling of data streams using coded preambles. An embodiment of an apparatus includes an interface with a communication channel, transmitter coupled with the interface to transmit one or more data streams via the interface, and a processing element, the processing element to receive one or more data streams for transmission. Upon receiving multiple data streams for transmission of a first type of data, including a first data stream and a second data stream for transmission of the first type of data, the processing element is to select a first preamble for the first data stream and a second preamble for the second data stream, where the first preamble is distinguishable from the second preamble.

Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

Abstract: A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image. The best phase may represent the image such that the image is displayed in a manner in accordance with human vision perceptions.

Abstract: Embodiments of the invention are generally directed to integration of signal sampling within a transistor amplifier stage. An embodiment of an apparatus includes a amplifier stage including a transistor to receive a source signal and produce an output signal, wherein the transistor includes multiple fingers for at least a first electrode of the transistor. The amplifier stage uses connections to some of the fingers of the first electrode for production of the output signal, and uses one or more other fingers for the first electrode of the transistor for a separate function from the production of the output signal.

Abstract: Embodiments of the invention are generally directed to performing processing of content through partial authentication of secondary channel. An embodiment of a method includes performing a first authentication between a source transmitting device and a sink receiving device for communication of data streams, and performing a second authentication between the source transmitting device and a bridge device such that the second authentication is independent of the first authentication and the sink receiving device remains uninfluenced by the second authentication. The bridge device includes an intermediate carrier device coupled to the source transmitting device and the sink receiving device. The method further includes transmitting a data stream having encrypted content from the source transmitting device to the bridge device.

Abstract: In some embodiments, an apparatus includes device functional circuitry to perform at least one service; and network interface control circuitry to control interaction between the apparatus and a network. The network interface control circuitry includes a service discovery module to (1) send a presence announcement message to be transmitted outside the device to let other devices outside the device know of services the device may perform and (2) to receive presence announcement messages from the other devices outside the device to learn what services to the other devices may perform. In some embodiments, the network interface control circuitry includes a dynamic connection management module. Other embodiments are described and claimed.

Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.

Abstract: A method and apparatus is disclosed herein for providing a connection between a connector and a flex cable. In one embodiment, the connector scheme comprises: a flex ribbon having first and second sides, the first side being opposite the second site, where the flex ribbon has one or more traces on the first side and a ground plane on at least a portion of the second side; and a connector into which the flex ribbon is inserted to make an electrical connection thereto, where the connector has a metal shell in electrical contact with the ground plane while having contacts in electrical contact with the one or more traces.

Abstract: A mechanism for facilitating dynamic synchronization of audio and video for multiple media devices is described. In one embodiment, an apparatus includes first logic to insert a signature in an audio portion of an audio/video data stream. The signature represents uniquely identifiable data and is to be transmitted to a second media device having a display device. The apparatus may include second logic to detect the signature in the audio portion of the audio/video data stream, third logic to calculate latency of the display device using an audio output of the display device, and fourth logic to synchronize the audio output to a corresponding video display based on a feedback loop generated using the audio portion of the audio/video data stream transmitted to the display device and the audio output of the display device.

Abstract: A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Abstract: The present disclosure is related to a hardware component for communications over a multimedia communication interface. In one embodiment, a hardware component includes a disparity circuit that stores a disparity value. The disparity value indicates the disparity between the number of “1”s and the number of “0”s previously transmitted by the hardware component. The hardware component also includes circuitry for receiving multimedia data to be scrambled, encoded and transmitted by the hardware component. In one embodiment, the multimedia data includes video data and data island data. In one embodiment, the hardware component generates transition minimized intermediate codes based on values in the guard band data included within the video data and data island data. The hardware component generates encoded guard band codes that are transition minimized as well as direct current balanced. The hardware component transmits the encoded guard band codes over a differential pair of the multimedia communication device.

Abstract: Systems and methods for block noise detection and filtering are disclosed. One embodiment includes, computing difference magnitudes in pixel values for adjacent pixels in the image. The difference magnitudes can include horizontal difference magnitudes for horizontally adjacent pixels and vertical difference magnitudes for vertically adjacent pixels. One embodiment further includes using normalized sums of the difference magnitudes to determine a set of noise characteristics of the block noise and a set of image characteristics of the image and configuring inputs to the block noise filter using the set of noise and image characteristics.

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing. An embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel. The first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.

Abstract: A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

Abstract: A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video.

Abstract: A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator.

Abstract: Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.

Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.