Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.

Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: In at least one embodiment of the invention, a method of manufacturing an integrated circuit including a microelectromechanical system (MEMS) device includes forming a first structural layer above at least one semiconductor device formed on a substrate. The method includes forming a second structural layer above the first structural layer. The second structural layer has a thickness substantially greater than a thickness of the first structural layer. The MEMS device comprises at least one portion of at least one of the first and second structural layers. In at least one embodiment of the invention, the method is carried out at one or more temperatures less than a tolerable threshold temperature for the at least one semiconductor device.

Abstract: In one embodiment, a method can provide for dynamic updating of slope values used in determining a soft decision for a demodulated signal obtained in a receiver from a broadcast signal received by the receiver. The method includes generating a channel estimate for a channel traversed by the signal, computing channel state information from the channel estimate, computing statistical information from the channel state information, determining a slope value based at least in part on the statistical information, calculating a log-likelihood ratio (LLR) value for the signal, and applying the slope value to the LLR value to obtain a weighted LLR value.

Abstract: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.

Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

Abstract: An apparatus and a method for compensating for a mismatch in temperature coefficients of two oscillator frequencies to match a desired frequency ratio between the two oscillator frequencies over a temperature range. In one embodiment of a temperature sensor, first and second oscillators of different temperature characteristics are coupled to a differential frequency discriminator (DFD) circuit. The DFD circuit compensates for the different characteristics in order to match a frequency difference between the first and second frequencies over a temperature range.

Abstract: A MEMS structure having a temperature-compensated resonator member is described. The MEMS structure comprises an asymmetric stress inverter member coupled with a substrate. A resonator member is housed in the asymmetric stress inverter member and is suspended above the substrate. The asymmetric stress inverter member is used to alter the thermal coefficient of frequency of the resonator member by inducing a stress on the resonator member in response to a change in temperature.

Abstract: An apparatus for managing modem sample rates within a direct access arrangement (DAA) circuit is disclosed. The DAA circuit includes a serial audio interface for providing communications between the DAA circuit and a host computer system. The serial audio interface is capable of operating under multiple serial communication interface standards, such as the AC '97 standard and the HD Audio standard. The DAA circuit also includes means for configuring the serial audio interface to transmit and receive modem samples at an audio sample rate higher than a modem sample rate of modem samples and at a predetermined bit size that is wider than a bit size of the modem samples, such that one bit of each of the modem samples is utilized to indicate the validity of each associated modem samples.

Abstract: An apparatus for reducing modem command and status latency within a direct access arrangement (DAA) circuit is disclosed. The DAA circuit includes a serial audio interface for providing communications between the DAA circuit and the host computer system. The serial audio interface can operate under multiple serial communication interface standards, such as the AC '97 standard and the HD Audio standard. The DAA circuit also includes means for configuring the serial audio interface to transmit and receive modem samples at an audio sample rate higher than a modem sample rate of the modem samples and at a predetermined bit size that is wider than a bit size of the modem samples. The additional bits other than the modem samples are utilized to indicate command and status information associated with the DAA circuit or a telephone line such that modem command and status latency on the serial audio interface within the DAA circuit can be reduced.

Abstract: A non-echo canceling voice band modem capable of detecting subscriber alerting signal (SAS) tones and customer premises equipment alerting signal (CAS) tones is provided. The modem includes a shaping filter, an analog-to-digital converter (ADC), a SAS tone detector, a CAS tone detector and an echo canceler. The shaping filter, which is located in a transmitting path of the modem, filters modem signals to be transmitted from the modem. The ADC, which is located in a receiving path of the modem, converts any incoming analog signal to corresponding digital signals to be used by the modem. The echo canceler, which is coupled to the SAS and CAS tone detectors, cancels any echoes in modem signals before sending said modem signals to the SAS and CAS tone detectors.

Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Abstract: A low-noise block (LNB) control device within a set-top box is disclosed. The LNB control device is capable of controlling modulation of an alternating waveform on a direct current (DC) voltage from a DC power supply to an LNB amplifier. The LNB control device includes a power supply control module, an LNB signaling module and a switch. In response to a power supply feedback signal received from the DC power supply, the power supply control module sends a control signal to the DC power supply. In addition, the LNB signalling module provides a switch control signal and a modulating waveform to the switch. Under the control of switch control signal, the switch selectively sends the modulating waveform to a summing circuit that is located external to the LNB control device. Within the summing circuit, the modulating waveform is added to the DC voltage from the DC power supply.

Abstract: A method for handling data transmissions within a modem is disclosed. A codeword is generated by compressing one or more incoming characters. The incoming characters and codeword are subsequently stored in a buffer. Then, a cost difference between transmitting all the codewords previously stored in the buffer and transmitting all the characters previously stored in the buffer is updated based on the most recent codeword. If the determined cost difference is less than a low limit value, the characters previously stored in the buffer are transmitted. However, if the determined cost difference is greater than a high limit value, the codewords previously stored in the buffer are transmitted. Otherwise, if the determined cost difference falls inclusively between the low limit value and the high limit value, transmission of the buffered data is deferred until the cost difference is recalculated on the next codeword.

Abstract: An apparatus for controlling modulation of an alternating waveform on a direct current (DC) voltage signal within a low-noise block (LNB) controller is disclosed. The apparatus includes a DC power supply and a mixing/switching circuit. The DC power supply provides a steady DC voltage to a load, such as an LNB amplifier. The mixing/switching circuit adds a modulating signal to the DC voltage and selectively allows the modulated DC voltage to the load. The mixing/switching circuit includes a common control signal input for managing both of the above-mentioned two functions.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: A chopped intermediate frequency (IF) wireless receiver is disclosed. The wireless receiver includes a local oscillator (LO), a first and a second mixers, an LO frequency control module, an IF filter, a digital down converter and a down conversion controller. The LO provides a local oscillating signal to the first and second mixers. The first and second mixers converts a received radio frequency signal to an in-phase IF signal and a quadrature IF signal, respectively. The LO frequency control module alternately down converts a channel frequency by changing an oscillation frequency of the LO. Coupled to the digital down converter, the down conversion controller adjusts a complex sine wave within the digital down converter while the in-phase IF signal and the quadrature IF signal are being down-converted by the digital down converter to a baseband signal.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: Frequency modification circuitry may be employed as part of a crystal oscillator circuit to generate a reference signal with adjustable frequency. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may adjust the frequency of the reference signal in response to one or more frequency control signals. In one example, the frequency modification circuitry may include variable capacitors such as one or more continuously variable and/or discretely variable capacitors for providing coarse and/or fine adjustment of the reference signal frequency.