Abstract: An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.

Abstract: An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.

Abstract: A system and method for performing production testing on high power semiconductor devices is disclosed. The system includes signal generators, RF meters, sockets, couplers and connectors which also function as switches when connected to an external cable. A calibration process is executed which allows the controller to create a correlation between measurements taken by the RF meter and the actual voltages, and power levels present at the device under test. By performing this calibration, it is possible to perform production testing of devices much more quickly and reliably.

Abstract: In at least one embodiment, a method for measuring a distance between a first communications device including a first local oscillator and a second communications device including a second local oscillator includes unwrapping N phase values to generate N unwrapped phase values. N is an integer greater than one. Each of the N phase values indicate an instantaneous phase of a received signal. The method includes averaging the N unwrapped phase values to generate an average phase value. The method includes wrapping the average phase value to generate a final phase measurement of the first local oscillator with respect to the second local oscillator.

Abstract: A system having a locator device and a plurality of tag devices is disclosed. The locator device comprises an antenna array allowing it to determine an angle of arrival for incoming signals from each of the plurality of tag devices. The system also defines a sequence of time slots, where each time slot has a specific function. The sequence may start with a locator time slot, where the locator device transmits a packet that informs all of the tag devices that this is the start of the sequence. A sync slot follows the locator time slot, where new tag devices may transmit a sync request to the locator device. Upon receipt of a sync request, the locator device assigns the new tag device a tag slot. Following the sync slot are a plurality of tag slots, where each tag device transmits an AoA packet during its assigned tag slot.

Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.

Abstract: A system and method for determining a position or a movable device is disclosed. The present system utilizes a movable device equipped with a locator device that has an antenna array such that it may determine the angle of arrival of a plurality of incoming beacon signals. In certain embodiments, the movable device is also able to measure its distance travelled. By knowing its distance moved and the angle of arrival from each beacon, the locator device is able to calculate its position as well as the position of each beacon. This procedure may be executed at regular intervals so that the movable device accurately determines its position.

Abstract: In one embodiment, a method includes: laser ablating an encapsulant of a semiconductor package, until a threshold amount of the encapsulant remains above one or more die of the semiconductor package; and providing at least one drop of acid onto a surface of the ablated semiconductor package to acid etch for a first time duration, to remove a remaining portion of the encapsulant above the one or more die, where after the acid etch, a die of interest is exposed and the silver bond wires of the semiconductor package are preserved.

Abstract: A BLE system includes a network controller, peripherals, and central. As one of the peripherals begins to roam, the current central device in a connection with the peripheral detects when the peripheral device is moving away from the current central. Other centrals receive requests to perform coordinated sensing of transmissions from the peripheral device to the current central device. The coordinated sensing includes the other central devices monitoring transmissions from the peripheral device to determine respective received signal strength indicators (RSSIs) on at least one frequency corresponding to a frequency hopping pattern of the connection. The other centrals report the coordinated sensing results to the network controller which determines a next central based, at least in part, on the sensed RSSIs. The network controller sends blacklists to centrals that are not the next central and the peripheral disconnects from the current central, advertises, and reconnects with the next central.

Abstract: A method for operating a switched-mode power converter includes providing to a maximum voltage node as a maximum voltage, a version of the higher of a first voltage on a first node and a second voltage on a second node. The method includes generating a first signal indicating whether to operate the switched-mode power converter in a buck mode of operation or a boost mode of operation based on the first voltage and a first voltage domain based on the maximum voltage. The method includes generating a second signal indicating whether to operate the switched-mode power converter in a buck mode of operation or a boost mode of operation based on the first voltage and a second voltage domain of the first voltage. The method includes combining the first signal and the second signal to generate a digital configuration indicator signal.

Abstract: In one aspect, an apparatus includes an oscillator to generate a clock signal, where the oscillator includes: at least one resistor; at least one capacitor; and a circuit coupled to the at least one resistor and the at least one capacitor, the circuit to generate the clock signal. The apparatus further includes a voltage regulator coupled to the oscillator to provide a regulated voltage to the oscillator, and a bulk voltage generator coupled to the voltage regulator. The bulk voltage generator may provide first and second bulk voltages to the voltage regulator to provide temperature compensation to the oscillator.

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

Abstract: In one aspect, an inductor may include at least one loop formed on a first metal layer and a non-uniform introduced pattern formed on the first metal layer and circumscribed by the at least one loop. The non-uniform introduced pattern may be formed of a plurality of structures and may have a maximum density at an interior portion thereof and a minimum density at a peripheral portion thereof, where at least some of the plurality of structures have different sizes.

Abstract: An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

Abstract: Techniques for quickly and accurately determining whether a channel is being used for transmission of data using one of a plurality of communications protocols for low power signals using random data of a packet are disclosed. The techniques increase sensitivity and reduce the false alarm rate for a wide range of signal and noise levels. A noise detection technique uses an adaptive window size for fast noise detection that increases the rate of scanning channels during a signal identification period. In a BLE1M detection mode, detection of clusters of zero frequency deviation are used to reduce the false detection rate. Adaptive Zigbee symbol detection improves detection sensitivity beyond ?97 dBm. The techniques use a chip-based differential to generate frequency deviation samples for Zigbee detection or data filtering frequency deviation samples generated using sample-based differentials based on an oversampled received signal to improve the signal-to-noise ratio.

Abstract: An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

Abstract: In an embodiment, an apparatus includes: a sensor to sense real world information; a digitizer coupled to the sensor to digitize the real world information into digitized information; a signal processor coupled to the digitizer to process the digitized information into an image; a discriminator coupled to the signal processor to determine, based at least in part on the image, whether the real world information comprises an anomaly, where the discriminator is trained via a generative adversarial network; and a controller coupled to the discriminator.

Abstract: A cluster correlator may be configured with: a first stage comprising a set of first correlators to correlate samples of an input signal with a first predetermined pattern and output an output sample, the set of first correlators to output a sample cluster corresponding to the output sample of the set of first correlators during a switching cycle of the first stage; a filter coupled to an output of the first stage to receive the sample cluster and to produce a processed output sample based on the sample cluster; and a second stage comprising at least one second correlator to receive a processed output sample from the filter and correlate the processed output sample with a second predetermined pattern, and output one or more correlation outputs during a switching cycle of the second stage.