Abstract: A method includes supplying a current to at least one conductive path integral with a MEMS device to thereby exert a Lorentz force on the MEMS device in the presence of a magnetic field. The method includes determining the magnetic field based on a control value in a control loop configured to maintain a constrained range of motion of the MEMS device. The control loop may be configured to maintain the MEMS device in a stationary position. The current may have a frequency equal to a resonant frequency of the MEMS device.

Abstract: A power supply including a switching voltage regulator detects a peak power fault if a peak power limit is exceeded during a switching cycle of the voltage regulator. A second fault condition exists if a second power limit, lower than the peak power limit, is exceeded over a second time period, longer than the first time period. The switching voltage regulator is stopped in response to either the first or the second fault condition. Responsive to the second fault condition, the switching voltage regulator may be stopped until AC power is cycled or until a predetermined time period has elapsed.

Abstract: An apparatus includes a first conductive loop coupled to conduct a first current and a second conductive loop coupled in parallel with the first conductive loop and further coupled to conduct a second current. A first conductive portion forms a part of the first conductive loop and the second conductive loop. The first conductive portion is coupled to conduct the first current and the second current. In at least one embodiment of the apparatus, the first conductive loop and the second conductive loop are planar inductors formed in a conductive layer on a substrate of an integrated circuit.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: An electrostatic discharge (ESD) protection circuit apparatus is disclosed. The apparatus includes activation circuitry coupled to a first node. The activation circuitry includes a capacitor and a selectable load. A time constant ? associated with the activation circuitry varies in accordance with the selectable load. The activation circuitry is configured to provide ?=?1 for detection of an ESD event. A shunt is selectively enabled by the activation circuitry to short the first node to a second node in accordance with the detection of the ESD event. The activation circuitry is configured subsequent detection of the ESD event to provide ?=?2, wherein ?2>?1.

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Abstract: A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods.

Abstract: In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry.

Abstract: In one embodiment, a method can provide for dynamic updating of slope values used in determining a soft decision for a demodulated signal obtained in a receiver from a broadcast signal received by the receiver. The method includes generating a channel estimate for a channel traversed by the signal, computing channel state information from the channel estimate, computing statistical information from the channel state information, determining a slope value based at least in part on the statistical information, calculating a log-likelihood ratio (LLR) value for the signal, and applying the slope value to the LLR value to obtain a weighted LLR value.

Abstract: An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

Abstract: A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures.

Abstract: A brown out detector (BOD), configured to provide a BOD reset in the event of a brown out event, is provided. The BOD includes means for tracking a reference voltage that is updated through duty cycling schemes so as to reduce power consumption, as well as means for detecting a falling flank of a supply voltage so as to optimize response times. More specifically, the BOD includes at least one track module, at least one sample module, at least one detector module and at least one comparator. The comparator is configured to compare a duty cycled tracked reference voltage with a duty cycled sampled reference voltage and to output a BOD reset if the tracked reference voltage is less than the sampled reference voltage. The comparator is further capable of exhibiting improved response times when a boost current is received. The boost current is provided by the detector module when the supply voltage falls beyond a predetermined threshold.

Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.

Abstract: A receiver circuit includes an asynchronous demodulator having a demodulator input to receive a first signal and a demodulator output configured to provide a demodulated signal. The receiver circuit further includes a circuit, a multiplexer, and a synchronous demodulator. The modulator circuit includes a modulator input coupled to the demodulator output and includes a modulator output. The modulator re-modulates the demodulated signal to produce a second signal and provides the second signal to the modulator output. The multiplexer includes a first input to receive the first signal, a second input coupled to the modulator output to receive the second signal, a control input to a receive a select signal, and a multiplexer output. The synchronous demodulator includes an input coupled to the multiplexer output and an output to provide a demodulated output signal corresponding to a selected one of the first signal and the second signal.

Abstract: A circuit includes an input terminal and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode string formed from a plurality of P-N junction devices arranged in series. The diode string includes an input coupled to the input terminal and includes at least one output coupled to a power supply terminal. The circuit further includes a plurality of shunt elements. Each of the plurality of shunt elements includes a first terminal coupled to one of the plurality of P-N junction devices and a second terminal coupled to the power supply terminal. Each of the plurality of shunt elements is controllable to selectively couple the one of the plurality of P-N junction devices to the power supply terminal to distribute current flow across the diode string in response to an ESD event.

Abstract: A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal.

Abstract: A method of forming a microelectromechanical systems (MEMS) device includes forming an electrode on a substrate. The method includes forming a structural layer on the substrate. The structural layer is disposed about a perimeter of the electrode and has a residual film stress gradient. The method includes releasing the structural layer to form a resonator coupled to the substrate. The residual film stress gradient deflects a first portion of the resonator out of a plane defined by a surface of the electrode.

Abstract: An integrated circuit includes a current-based digital-to-analog converter (IDAC) including a clock input and including an output. The integrated circuit further includes a sample synchronization generator to provide a clock signal to a clock output terminal and a first timing signal related to the clock signal to the clock input of the IDAC. The sample synchronization generator controls the clock signal and the first timing signal to communicate a control signal to a peripheral module.

Abstract: In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.