Abstract: In one embodiment, the present invention includes a method for filtering an incoming signal in a channel filter of an automatic frequency control (AFC) loop to obtain a filtered incoming signal, generating a frequency offset from the filtered incoming signal in the AFC loop, removing the frequency offset from the incoming signal to obtain an adjusted signal, and providing the adjusted signal to an input of the channel filter.

Abstract: A system includes a cellular radio and an FM transmitter that are fabricated in the same semiconductor. The FM transmitter includes at least one mixer, a filter and an antenna tuning network. The mixer(s) translate an intermediate carrier frequency of an input signal to generate a second signal that has an FM carrier frequency. The filter removes spectral energy from the second signal to generate a third signal. The antenna tuning network is separate from the filter and produces a fourth signal to drive an antenna in response to the third signal.

Abstract: In one embodiment, the present invention includes a method for executing an application to perform voice over Internet protocol (VoIP) telephony, requesting a hardware key from a line interface device, comparing the hardware key to a software key associated with the application, and enabling the VoIP telephony if the keys match.

Abstract: An apparatus and a method for compensating for a mismatch in temperature coefficients of two oscillator frequencies to match a desired frequency ratio between the two oscillator frequencies over a temperature range. In one embodiment of a temperature sensor, first and second oscillators of different temperature characteristics are coupled to a differential frequency discriminator (DFD) circuit. The DFD circuit compensates for the different characteristics in order to match a frequency difference between the first and second frequencies over a temperature range.

Abstract: An integrated circuit package includes a DC/DC boost converter for providing an output voltage at a program level to associated components of the integrated circuit package. The DC/DC boost converter includes a first mode of operation wherein the DC/DC boost converter is enabled responsive to an input battery voltage falling below a programmed level of the output voltage. The DC/DC boost converter also includes a second mode of operation wherein the DC/DC boost converter is disabled responsive to the input battery voltage being above the programmed level of the output voltage.

Abstract: In a particular embodiment, a method includes receiving a powered device (PD) detection signal at a PD from a powered network and applying the PD detection signal to an external resistor to provide a detection signature to the powered network. Further, the method includes receiving a PD classification mark signal at the PD, applying the received PD classification mark signal to the external resistor, and selectively activating a classification mark current path in parallel with the external resistor to produce a classification mark signature.

Abstract: Image rejection factors are calibrated for a receiver circuit (106) during an initialization period. The image rejection factors are stored in a quasi non-volatile memory (124) associated with the receiver circuit (106). The quasi non-volatile memory (124) is powered from a first source (VDD A) during a first receiver mode and from a second source (VIO) during a second receiver mode.

Abstract: A low-noise amplifier includes a first resistor that receives a first signal of a differential input signal, and a second resistor that receives a second signal of the differential input signal. The amplifier includes a first transconductance device coupled to the first resistor that provides a first signal of a differential output signal, and a second transconductance device coupled to the second resistor, that provides a second signal of the differential output signal. The receiver also includes a first capacitor coupled between the first resistor input and a control electrode on the second transconductance device, and a second capacitor coupled between the second resistor input and a control electrode on the first transconductance device. The low-noise amplifier can include additional gain stages.

Abstract: In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.

Abstract: A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Abstract: In one embodiment, the present invention includes an operational amplifier having a first input to receive a first current formed of an input current and an offset current. A first MOSFET device having a gate terminal may be coupled to an output of the operational amplifier. An output stack including one or more cascoded devices to provide an output current corresponding to a gain of the operational amplifier may be coupled to a first terminal of the first MOSFET device. The operational amplifier may be used in various circuitry, such as a subscriber line interface circuit (SLIC).

Abstract: A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: In a particular embodiment, a circuit device includes a plurality of programmable voltage regulator circuits adapted to produce one or more unique power supplies. Each programmable voltage regulator circuit includes a power supply output terminal and a base regulator circuit module that has multiple configurable parameters to support a plurality of regulator configurations. The base regulator circuit module includes a plurality of leads. Each programmable voltage regulator circuit further includes selected circuitry coupled to the plurality of leads and to the power supply output terminal. The selected circuitry is adapted to cooperate with the base regulator circuit module to provide a selected type of regulator circuit and to apply a power supply to the power supply output terminal.

Abstract: In one embodiment, a method provides multiple-tone wideband I/Q mismatch calibration. A plurality of calibration frequencies is selected within a channel. A calibration tone is applied to the channel at each of the plurality of calibration frequencies. An I/Q mismatch is estimated at each of the plurality of calibration frequencies. An n-th order filter is constructed to compensate received signals relative to the estimated I/Q mismatch related to each calibration frequency.

Abstract: A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer.

Abstract: In a particular embodiment, a circuit device is disclosed that includes a power sourcing equipment (PSE) circuit having a plurality of high-voltage line circuits adapted to communicate with a respective plurality of powered devices via network cables. The PSE circuit includes a serial interface circuit and includes a common controller coupled to the serial interface circuit and to the plurality of high-voltage line circuits. The circuit device also includes a low-voltage circuit having a programmable controller adapted to transmit control signals to the common controller via the serial interface circuit to control operation of the plurality of high-voltage line circuits.

Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.

Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.

Abstract: Methods and systems for determining transmission channels for short range transmissions are disclosed. A transmitter provides short range transmission to a broadcast receiver configured to receive and tune channels within a signal spectrum. Channels within the broadcast signal spectrum are scanned, and an indication of received signal strength is obtained for each channel. The received signal strength indication (RSSI) can then be compared to a threshold power level that correlates to a signal level that the transmitter will be capable of overpowering based upon the transmission power of the transmitter. The scan results in an indication of one or more channels that have received signal strengths below the threshold power level of the transmitter.