Abstract: In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.

Abstract: In one embodiment, the present invention includes a slot antenna that is formed on a ground plane of a circuit board. The slot antenna may be connected to radio circuitry adapted on the circuit board by way of a feedline, which is coupled to the radio circuitry and across a portion of the slot antenna.

Abstract: According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data.

Abstract: In a particular embodiment, a power sourcing equipment (PSE) device is disclosed that includes a plurality of network input/output (I/O) interfaces adapted to physically and electrically connect to a respective plurality of cables. The PSE device further includes a plurality of driver circuits. Each driver circuit of the plurality of driver circuits is coupled to a respective network I/O interface of the plurality of network I/O interfaces to send and receive data via a respective cable of the respective plurality of cables. Further, the PSE device includes a shared isolation barrier to electrically isolate control circuitry from the plurality of driver circuits.

Abstract: A magnetically differential input circuit is arranged to define at least two loops, wherein each of the loops traverses the input of a receiving circuit. The loops are physically arranged so that a source of interference induces opposing signals in the loops, thereby effecting cancellation of the interference at the input of the receiving circuit. In one embodiment, the input circuit is arranged to be electrically differential as well as magnetically differential.

Abstract: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.

Abstract: An asynchronous receiver system has multiple antennae and an asynchronous receiver circuit with a signal input. The asynchronous receiver circuit receives a wireless signal at the signal input and generates a first quality signal responsive to the received wireless signal. A switch selects one of the antennae for coupling to the input of the asynchronous receiver circuit responsive to a control signal. A controller receives the first quality signal and generates the switching control signal. The controller sequentially selects each one of the antennae, measures the first quality signal and starts a timer with a time value for the selected antenna. The controller selects a next one of the antennae if the measured first quality signal value is below a threshold value and the timer expires and receives a remainder of a data packet based on the measured first signal quality values for the plurality of antennae.

Abstract: An integrated circuit having voltage isolation capabilities includes a first area of the integrated circuit containing functional circuitry that is located in the substrate of the integrated circuit. A second area of the integrated circuit contains an integrated RF isolation circuitry for voltage isolating the functional circuitry. The RF isolation circuitry is located in the metal layers of the integrated circuit.

Abstract: A powered device includes an interface that is responsive to a powered network and an integrated circuit device that is coupled to the interface to receive power and data from the powered network. The integrated circuit device includes a power rectification and protection device to generate a rectified power supply related to the power received from the interface, a switching regulator to selectively activate a switched power supply to associated load circuitry, and a power over Ethernet (PoE) controller. The PoE controller controls the switching regulator to provide the switched power supply to the associated load circuit when the rectified power supply is within an operating range.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A dual in-situ mixing approach for extended tuning range of resonators. In one embodiment, a dual in-situ mixing device tunes an input radio-frequency (RF) signal using a first mixer, a resonator body, and a second mixer. In one embodiment, the first mixer is coupled to receive the input RF signal and a local oscillator signal. The resonator body receives the output of the first mixer, and the second mixer is coupled to receive the output of the resonator body and the local oscillator signal to provide a tuned output RF signal as a function of the frequency of local oscillator signal.

Abstract: An integrated low-IF (low intermediate frequency) terrestrial broadcast receiver and associated method are disclosed that provide an advantageous and cost-efficient solution. The integrated receiver includes a mixer, local oscillator generation circuitry, low-IF conversion circuitry, and DSP circuitry. And the integrated receiver is particularly suited for small, portable devices and the reception of terrestrial audio broadcasts, such as FM and AM terrestrial audio broadcast, in such portable devices.

Abstract: A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level.

Abstract: A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART.

Abstract: A single chip radio platform is disclosed for communicating with an RF channel. An RF front end is provided having a receive/transmit capability to receive an RF carrier modulated with digital data and convert the data to analog baseband data, and modulate an RF carrier with baseband data. A digital signal processor (DSP) engine is provided for interfacing with the RF front end to form in conjunction therewith the PHY layer, and interfacing with the MAC layer to demodulate the baseband data and in the transmit mode to generate the baseband data for modulation and transmission by the RF front end. A microcontroller unit (MCU) is provided for performing the functionality of the MAC, network and application layers and interfacing with the DSP.

Abstract: An isolator provides bidirectional data transfer for a plurality of communications channels. First and second dies are located on first and second sides of a voltage isolation barrier and have a first and second plurality of digital data input/output pins associated therewith. First circuitry on the first die and third circuitry on the second die serializes a plurality of parallel digital data inputs from the digital data input/output pins onto one link across the barrier and transmits synchronization clock signals associated with the digital data inputs over a link across the barrier. Second circuitry on the second die and fourth circuitry on the first die de-serializes the digital data inputs from the first link onto the second digital data input/output pins and receives the first synchronization clock signal associated with the digital data inputs on the second link.

Abstract: A voltage regulator circuit comprises an error amplifier for generating an error signal responsive to a reference voltage in a feedback signal. A feedback circuit provides the feedback voltage signal to the error amplifier and a driver circuit provides regulated output voltage responsive to the input voltage in the error signal. Short circuit protection circuitry selectively protects transistors within the error amplifier, the feedback amplifier and the driver circuit responsive to a short circuit protection enablement signal.

Abstract: In one embodiment, the present invention includes a digital mixer to receive and digitally mix incoming weather band radio data with a control signal, a digital demodulator to demodulate the data to obtain a demodulated signal, and a digital feedback loop coupled between the demodulator and the digital mixer. The digital feedback loop includes a loop filter to receive the demodulated signal and to generate a filtered output and a fine tune controller to receive the filtered output and a frequency control signal and to generate the control signal based on them. In this way, audible artifacts caused by a frequency step change occurring in an analog front end to which the digital circuitry is coupled can be reduced or removed.

Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Abstract: A communication device is disclosed having optical and near-field communication capability. The device includes an optical transceiver circuit fabricated on an integrated circuit die and configured to transmit and receive far field signals. A near field transceiver circuit is also fabricated on the integrated circuit die and is configured to transmit and receive near-field electro-magnetic signals. Control circuitry is provided to selectively enable the optical transceiver circuit and the near field transceiver circuit responsive to an external control signal.