Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

Abstract: Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.

Abstract: Numerous examples are disclosed of an improved grouping and error correction system for non-volatile memory cells. In one example, a system comprises a memory array comprising non-volatile memory cells arranged into rows and columns, wherein a non-volatile memory cell of the memory array stores a first bit of a first data grouping and a second bit of a second data grouping, and wherein the first grouping is backed by a first ECC block and the second grouping is backed by a second ECC block.

Abstract: Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.

Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

Abstract: In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

Abstract: In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.

Abstract: A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

Abstract: A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.