Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m?2u, n?2v, and p?2t.

Abstract: Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Abstract: A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

Abstract: A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

Abstract: A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract: A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.