Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

Abstract: A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system comprises an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

Abstract: An improved low-power sense amplifier for use in a flash memory system is disclosed. The reference bit line and selected bit line are pre-charged during a limited period and with limited power consumed. The pre-charge circuit can be trimmed during a configuration process to further optimize power consumption during the pre-charge operation.

Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.