Patents Assigned to Silicon Storage Technology, Inc.
  • Method and apparatus for data refresh for analog non-volatile memory in deep learning neural network
    Patent number: 10861568
    Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
    Patent number: 10860918
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Charge pump for use in non-volatile flash memory devices
    Patent number: 10847227
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Programming of memory cell having gate capacitively coupled to floating gate
    Patent number: 10838652
    Abstract: A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Viktor Markov, Alexander Kotov
  • Dynamic modification of programming duration based on number of cells to be programmed in analog neural memory array in deep learning artificial neural network
    Patent number: 10839907
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Method of making split gate non-volatile flash memory cell
    Patent number: 10833178
    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 10, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
  • Method of making split gate non-volatile flash memory cell
    Patent number: 10833179
    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 10, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
  • Split gate non-volatile memory cells and logic devices with FINFET structure, and method of making same
    Patent number: 10818680
    Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 27, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Feng Zhou, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
  • Neural network classifier using array of four-gate non-volatile memory cells
    Patent number: 10803943
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 13, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Level shifter for integrated circuit
    Patent number: 10804902
    Abstract: An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved level shifter comprises a coupling stage and a level-switching stage.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 13, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Ryan Mei, Claire Zhu, Xiaozhou Qian
  • FinFET-based split gate non-volatile flash memory with extended source line FinFET, and method of fabrication
    Patent number: 10797142
    Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 6, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
  • Method of making embedded memory device with silicon-on-insulator substrate
    Patent number: 10790292
    Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 29, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steven Lemke, Nhan Do
  • Adaptive high voltage circuitry and methods for programming operations in an analog neural memory array in a deep learning artificial neural network
    Patent number: 10790022
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: September 29, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof
    Patent number: 10755779
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
    Patent number: 10748630
    Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Steven Lemke, Santosh Hariharan, Stanley Hong
  • Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
    Patent number: 10741568
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Flash memory cell and associated decoders
    Patent number: 10741265
    Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 11, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Memory device and method for varying program state separation based upon frequency of use
    Patent number: 10720217
    Abstract: A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 21, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Non-volatile split gate memory cells with integrated high K metal control gates and method of making same
    Patent number: 10714634
    Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
  • Method of programming a split-gate flash memory cell with erase gate
    Patent number: 10714489
    Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Yuri Tkachev, Alexander Kotov, Nhan Do