Abstract: The present disclosure relates to a method for controlling thermal radiation from a component. The method involves arranging a thermally conductive base layer in contact with the component, the base layer including a thermally emissive surface. A plurality of independently controlled shutter elements are movable about at least two orthogonal axes, and between closed and open positions, to change a dimension of a gap separating edges of adjacent ones of the shutter elements. The movements of the shutter elements are controlled about the two orthogonal axes to control the dimensions of the gaps to control thermal radiation emitted through the gaps.

Abstract: The present disclosure relates to an optical sensor protection system. The system may have a sensor for receiving an incoming optical signal, a passive sensing and modulation component, and an active sensing and modulation subsystem. The passive sensing and modulation component is configured to sense when a first characteristic is associated with the incoming optical signal is present that adversely affects operation of the sensor, and redirects at least a portion of the incoming optical signal thereof away from the sensor to thus reduce an intensity of the incoming optical signal reaching the sensor. The sensor is located on an image plane downstream of the ISM subsystem, relative to a path of travel of the incoming optical signal.

Abstract: The present disclosure relates to a thermal emissivity control system. The system may have a segmented array that makes use of a thermally conductive base layer configured to be connectable to an external heat generating subsystem, with the base layer including a thermally emissive surface. The array may also have a plurality of actuation elements at least one of positioned on or adjacent to the thermally emissive surface. A plurality of movable shutter elements is disposed adjacent one another in a grid pattern, and controlled in movement by the actuation elements to create gaps of controllably varying dimension therebetween. The shutter elements control at least one of a magnitude of, or direction of, thermal radiation through the gaps.

Abstract: The present disclosure relates to a system for modifying temporal dispersion in an optical signal. The system makes use of a segmented array including a plurality of independently controllable, reflective optical elements. The optical elements are configured to segment a received input optical signal into a plurality of beamlets, and to reflect and steer selected ones of the plurality of beamlets in predetermined angular orientations therefrom. A variable optical dispersion subsystem is used which has a plurality of optical components configured to receive and impart different predetermined time delays to different ones of the received beamlets, and to output the plurality of beamlets therefrom.

Abstract: Methods for generating a cell set for an analog design tool are disclosed. A method comprises receiving, at a cell generator, one or more electronic files of a process-specific architectural cell (AP_Cell) having wiring for power and ground, FILL, wherein the AP_Cell is configured according to a first manufacturing process. The method further includes receiving, at the cell generator, one or more electronic files of a schematic cell (S_Cell) having internal wiring between circuit elements to provide a function for the S_Cell. The method also includes merging data from the one or more electronic files of the AP_Cell and the one or more electronic files of the S_Cell to generate a process-specific schematic cell (SP_Cell) used as a building block for a physical layout of an analog IC, wherein the process-specific schematic cell comprises one or more electronic files. Related devices are also described herein.

Abstract: A method for designing a semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by an analog circuit designer using an analog design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Abstract: A method for designing an semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This consumes less power for a read operation. Senseamps for finally converting low-level signals to full logic output voltage levels are located right next to output buffers and data output pads for the SRAM. The bit lines for a memory CORE are formed in lower metal layers that are closer to the core memory cells and, thus, have higher capacitance. The present invention uses lower-capacitance top layers 4–6 of a 6 metal layer scheme for the signal lines of the differential internal data bus. An optimum configuration has the capacitance of a bitline equal to the capacitance of the differential internal data bus bit-line.

Abstract: An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a second input circuit. The first input circuit receives a first input signal from a connected circuit and the second input circuit receives a second signal from the connected circuit. A first current mirror receives signals from the first input circuit of said folded cascode. A second current mirror receives signals from the second input circuit. The first current mirror and the second current mirror are connected to a common output to merge signals from the first and second input circuits. A diode adjusts a voltage level of the signals to an output voltage.

Abstract: Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.

Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.

Abstract: An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer includes at least one slot that removes conductive material from the bus. The removal of the conductive material in the slot allows the space between circuitry adjacent the bus and the bus to be reduced.

Abstract: To alleviate the crosstalk between BL and BLN of the same column, the present invention provides vertical twisting for the bit line and the complementary bit line of a line pair connecting a column of memory bits to a sense amplifier. The BL and BLN run in the same direction, but never within same metal layer and never overlying each other. To provide vertical twisting, horizontal and vertical switching are done in the same crossover channels so that BL and BLN have the same length in order to keep the overall capacitance of each line the same. Triple standard twist regions can be used for both the horizontal and vertical twists. The capacitance between BL and BLN are substantially reduced as well as the capacitance to neighboring column BLs and BLNs. Capacitive coupling between a BL and a BLN of the same column is reduced to thereby prevent reduction of the voltage difference, or delta voltage, presented to the differential input terminals of a senseamp.

Abstract: A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

Abstract: An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer includes at least one slot that removes conductive material from the bus. The removal of the conductive material in the slot allows the space between circuitry adjacent the bus and the bus to be reduced.