Patents Assigned to Silicon Technologies, Inc.
  • Publication number: 20020176286
    Abstract: A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.
    Type: Application
    Filed: October 30, 2001
    Publication date: November 28, 2002
    Applicant: Virtual Silicon Technology, Inc.
    Inventors: Albert Bergemont, Gregorio Spadea
  • Publication number: 20020171103
    Abstract: A novel Laterally Diffused NMOS device is described. With proper design the drain terminal of this device can be raised to a much higher voltage that the maximum allowed gate voltage of the CMOS technology into which the device is built. The device can be built in a conventional deep submicron CMOS technology as used for the 0.25 um node and beyond without additional masks or dedicated processing steps. When a deep N-well mask and ion implantation is added to the process, the device can be operated with a body voltage positive above ground. This device can be used like a conventional LDMOS for circuits which require a device capable of switching voltages which exceed the rating of conventional CMOS devices by using as low voltage input signal.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 21, 2002
    Applicant: Virtual Silicon Technology, Inc.
    Inventor: Gregorio Spadea
  • Patent number: 6451652
    Abstract: A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: September 17, 2002
    Assignees: The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust, Virtual Silicon Technology, Inc.
    Inventors: John Caywood, Gregorio Spadea
  • Patent number: 4844105
    Abstract: An apparatus for cleaning and sealing the peripheral knife edge of a coke oven door has a vertical mast which is positioned adjacent one edge of a door suitably supported in vertical position on a door rack. A treatment carriage in the form a horizontal arm is mounted for vertical reciprocation along the mast. Spray heads are mounted on an endless conveyor chain looped around turning point sprockets at opposite ends of the treatment carriage. The diameter of the turning point sprockets and the distance therebetween are related to the curvature of the corners of the door and the width of the door so that as the drive chain traverses the upper part of its endless run the spray heads can spray a path corresponding to the profile of the top edge of the door and the curved corners at opposite ends thereof.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: July 4, 1989
    Assignee: Silicon Technology, Inc.
    Inventor: Joseph M. Evans