Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • Patent number: 12046494
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: July 23, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • Publication number: 20240234272
    Abstract: An electronic package is provided, in which a first electronic module and a second electronic module are stacked via a plurality of first conductive structures and a plurality of second conductive structures, and the amount of solder of the first conductive structures is greater than the amount of solder of the second conductive structures, such that the electronic package can be configured with the first conductive structures and the second conductive structures according to the degree of warpage of the electronic package, so as to effectively disperse the stress to avoid the problem of warpage.
    Type: Application
    Filed: December 12, 2022
    Publication date: July 11, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hung-Kai WANG, Yih-Jenn JIANG, Don-Son JIANG, Yu-Lung HUANG, Men-Yeh CHIANG
  • Patent number: 12033868
    Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: July 9, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shu-Chi Chang, Wei-Ping Wang, Hsien-Lung Hsiao, Kaun-I Cheng
  • Publication number: 20240222250
    Abstract: An electronic package is provided, in which a conductive structure and a reinforced insulation portion are bonded to a dielectric layer, and the reinforced insulation portion is in contact with and abuts against the conductive structure, such that the reinforced insulation portion can support the conductive structure to prevent the conductive structure from cracking when an electronic structure is disposed on the dielectric layer and electrically connected to the conductive structure.
    Type: Application
    Filed: May 2, 2023
    Publication date: July 4, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jun-Hao FENG, You-Chen LIN
  • Publication number: 20240222290
    Abstract: An electronic package is provided, in which an electronic element and a plurality of shielding pillars are embedded in an encapsulating layer, a shielding layer is formed on one surface of the encapsulating layer to cover the electronic element and is in contact with and connected to the plurality of shielding pillars, and a circuit structure is formed on the other surface of the encapsulating layer to electrically connect to the electronic element. Therefore, when the electronic package is disposed on a circuit board, the design of the shielding layer and the plurality of shielding pillars can provide the electronic element with heat dissipation and shielding effects without a metal cover arranged on the electronic element.
    Type: Application
    Filed: May 2, 2023
    Publication date: July 4, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Ching-Hung TSENG
  • Patent number: 12027753
    Abstract: An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 2, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Chu Lai, Ho-Chuan Lin, Min-Han Chuang
  • Patent number: 12027484
    Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: July 2, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20240213134
    Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier with a circuit layer, and an encapsulation layer encapsulating the electronic element has an opening exposing the circuit layer, where a metal structure can be contact-bonded on a wall surface of the opening, and a conductive element is formed on the metal structure and electrically connected to the circuit layer. Therefore, no gap is formed between the conductive element and the wall surface of the opening, such that the DC resistance of the conductive element can be reduced.
    Type: Application
    Filed: April 28, 2023
    Publication date: June 27, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Wei-Hao LI, Chih-Yi LIAO, Cheng-Wei HSU, Chih-Yuan TSAI, Ko-Wei CHANG, Guo-Yu WU
  • Publication number: 20240203900
    Abstract: An electronic package is provided, in which a first shielding part bonded with a first electronic component are disposed on a carrier structure, and the first electronic component and the first shielding part are covered by an encapsulation layer. The first shielding part includes a semiconductor block and a magnetized layer formed on the semiconductor block, and the first shielding part is bonded to the first electronic component, such that the semiconductor block separates the magnetized layer and the first electronic component. Therefore, a distance defined by a thickness of a single semiconductor block is maintained between the magnetized layer and the first electronic component, thereby preventing a magnetic field operation of the first electronic component from being interfered by a magnetic field of the magnetized layer.
    Type: Application
    Filed: April 11, 2023
    Publication date: June 20, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Jyun-Hao YANG, Chia-Yang CHEN
  • Patent number: 12014967
    Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: June 18, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai
  • Patent number: 12009340
    Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: June 11, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
  • Patent number: 12002737
    Abstract: An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 4, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pin-Jing Su, Cheng-Kai Chang
  • Publication number: 20240170415
    Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.
    Type: Application
    Filed: April 11, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240170355
    Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chien-Cheng LIN
  • Publication number: 20240162101
    Abstract: An electronic package includes a first electronic element and a dummy die embedded in an encapsulation layer, where the dummy die is used to prevent a warpage caused by the mismatch of coefficient of thermal expansion (CTE) between the encapsulation layer and the first electronic element in the manufacturing process of large full-panel.
    Type: Application
    Filed: March 27, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventor: Yung-Ta LI
  • Publication number: 20240162140
    Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Publication number: 20240162180
    Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Publication number: 20240162169
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Patent number: 11984393
    Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 14, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Patent number: 11984412
    Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: May 14, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang