Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • Patent number: 11410954
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 9, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11404361
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 11398429
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
  • Patent number: 11398413
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 26, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Publication number: 20220225493
    Abstract: An electronic device is provided, in which an antenna module for receiving and transmitting radiation signals is disposed on a mounting surface of a circuit board, and an inner layer of the circuit board is formed with a ground surface to arrange a strip-shaped ground circuit along the edges of the ground surface so that the ground circuit occupies at most 50% of the area of the ground surface to improve antenna radiation efficiency.
    Type: Application
    Filed: September 2, 2021
    Publication date: July 14, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ming-Fan Tsai, Chih-Wei Chen, Chien-Cheng Lin, Chao-Ya Yang, Chia-Yang Chen
  • Publication number: 20220214395
    Abstract: A control method is provided and used to place a target object on a test platform in a cabin of a testing device, to sense the temperature of the target object by a temperature response structure, and then to receive temperature signals of the temperature response structure by a controller, where the controller can regulate the pressure inside the cabin to control the air pressure of the cabin, so that the target object can still maintain good heat dissipation under high power consumption.
    Type: Application
    Filed: February 8, 2021
    Publication date: July 7, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Ming Tu, Chih-Ming Yang, Wen-Chin Liang, Cheng-Shao Chen, Yung-Ming Wang
  • Patent number: 11382214
    Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 5, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lung-Yuan Wang, Wen-Liang Lien
  • Patent number: 11380978
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes stacking an antenna board on a circuit board, and disposing between the antenna board and the circuit board a supporting body securing the antenna board and the circuit board. As such, during a packaging process, the distance between the antenna board and the circuit board is kept unchanged due to the supporting body, thus ensuring that the antenna board operates properly and improving the product yield.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 5, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shi-Min Zhou, Han-Hung Chen, Rung-Jeng Lin, Kuo-Hua Yu, Chang-Fu Lin
  • Publication number: 20220196731
    Abstract: Provided is a testing method including: disposing a wafer on a working platform of a testing device; and moving a circuit board of the testing device relative to the working platform by a movement assembly of the testing device so as to allow at least two testing ports of the circuit board to test two chips of the wafer, respectively. Further, the two testing ports have different testing functions. Therefore, during the wafer testing process, a single testing device can perform multiple testing operations.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 23, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wen-Chin Liang, Po-Wen Hsiao, Cheng-Tsai Hsieh, Cheng-Shao Chen
  • Publication number: 20220189900
    Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 16, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yu Kuo, Rui-Feng Tai, Yih-Jenn Jiang, Don-Son Jiang, Chang-Fu Lin
  • Publication number: 20220181225
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 9, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220173052
    Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 2, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
  • Publication number: 20220148996
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20220148975
    Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
  • Publication number: 20220130769
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 28, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Chee-Key CHUNG
  • Patent number: 11315881
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
  • Patent number: 11289346
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 11289409
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 11289794
    Abstract: An electronic package is disclosed. An antenna board is stacked on a circuit board. A frame is formed on the circuit board. A supporter disposed between the antenna board and the circuit board is secured in the frame. In a packaging process, the frame ensures that the antenna board and the circuit board are separated at a distance that complies with a requirement, and that the antenna function of the antenna board can function normally.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: March 29, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Rung-Jeng Lin, Han-Hung Chen, Shi-Min Zhou, Kuo-Hua Yu, Chang-Fu Lin
  • Publication number: 20220093518
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 24, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang