Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • Patent number: 10461002
    Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
  • Patent number: 10461041
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing an electronic component on a lower side of a first carrier and forming an encapsulant on an upper side of the first carrier. A first conductor is disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation. As such, the electronic package has a reduced thickness and improved antenna efficiency.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chia-Yang Chen
  • Patent number: 10431535
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jui-Feng Chen, Chia-Cheng Hsu, Wen-Jung Tsai, Chia-Cheng Chen, Cheng Kai Chang
  • Patent number: 10410970
    Abstract: An electronic package is provided. An electronic component and a plurality of conductive pillars are provided on a carrier structure. An encapsulation layer encapsulates the electronic component and the conductive pillars. Each of the conductive pillars has a peripheral surface narrower than two end surfaces of the conductive pillar. Therefore, the encapsulation layer is better bonded to the conductive pillars. A method for fabricating the electronic package is also provided.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chia-Yang Chen
  • Patent number: 10403573
    Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Wei-Che Chang
  • Patent number: 10403567
    Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
  • Patent number: 10403570
    Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
  • Patent number: 10396040
    Abstract: An electronic package is provided, which includes: a carrier; a plurality of electronic elements disposed on the carrier; a bather frame disposed on the carrier and positioned between adjacent two of the electronic elements; an encapsulant formed on the carrier and encapsulating the electronic elements and the bather frame with a portion of the bather frame protruding from the encapsulant; and a shielding element disposed on the encapsulant and being in contact with the portion of the bather frame protruding from the encapsulant. Therefore, the electronic package has an electromagnetic interference (EMI) shielding effect improved. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yue-Ying Jian, Wei-Ping Wang, Tsung-Ming Li, En-Li Lin, Kaun-I Cheng, Yu-De Chu
  • Patent number: 10396021
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 27, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
  • Patent number: 10361150
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10340228
    Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 2, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
  • Patent number: 10325872
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10249562
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in the recess of the carrier; forming an insulating layer in the recess to encapsulate the electronic element; forming a circuit structure on the carrier, wherein the circuit structure is electrically connected to the electronic element; forming a plurality of through holes penetrating the carrier; and forming a conductive material in the through holes to form a plurality of conductors, wherein the conductors are electrically connected to the circuit structure. By using the carrier as a substrate body, the present invention avoids warping of the package structure.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 2, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Hsien-Wen Chen
  • Patent number: 10242972
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 26, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen, Guang-Hwa Ma, Cheng-Hsu Hsiao
  • Patent number: 10236261
    Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
  • Patent number: 10230152
    Abstract: An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the electronic element and the antenna structure. Therein, the antenna structure has an extension portion and a plurality of support portions connected to the extension portion for supporting the extension portion over the substrate so as to save the surface area of the substrate, thereby meeting the miniaturization requirement of the electronic package.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: March 12, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Heng-Cheng Chu, Chien-Cheng Lin, Tsung-Hsien Tsai, Chao-Ya Yang
  • Patent number: 10224243
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Patent number: 10199331
    Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Meng-Tsung Lee, Fu-Tang Huang
  • Patent number: 10199341
    Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang