Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • Publication number: 20240145403
    Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240145372
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Publication number: 20240145908
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and an antenna structure is stacked on the carrier structure via conductors, where at least one through hole is formed on and penetrating through the antenna structure, and an insulating support body is formed between the carrier structure and the antenna structure, so that the insulating support body is correspondingly formed at the through hole and/or an edge of the antenna structure, and the through hole is free from being filled up by the insulating support body, such that the through hole has an air medium. The design of the through hole allows the characteristic of the dielectric constant of air being 1 to be utilized so as to reduce the signal loss and the signal offset, thereby facilitating the signal transmission of the antenna body.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Chun LAI, Hsuan-Jen WANG, Rung-Jeng LIN
  • Publication number: 20240145455
    Abstract: An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Jie LEE, Chih-Nan LIN, Ci-Hong YAN, Nai-Hao KAO
  • Patent number: 11973014
    Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 30, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
  • Patent number: 11973047
    Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Patent number: 11973043
    Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai
  • Publication number: 20240136263
    Abstract: An electronic package is provided, in which a first electronic module and a second electronic module are stacked via a plurality of first conductive structures and a plurality of second conductive structures, and the amount of solder of the first conductive structures is greater than the amount of solder of the second conductive structures, such that the electronic package can be configured with the first conductive structures and the second conductive structures according to the degree of warpage of the electronic package, so as to effectively disperse the stress to avoid the problem of warpage.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 25, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hung-Kai WANG, Yih-Jenn JIANG, Don-Son JIANG, Yu-Lung HUANG, Men-Yeh CHIANG
  • Publication number: 20240128249
    Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 18, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chi-Ching HO
  • Publication number: 20240096835
    Abstract: A method of manufacturing an electronic package is provided, in which an electronic element is disposed on a carrier structure; a heat dissipation body of a heat dissipation structure is disposed on the electronic element via a heat dissipation material; the heat dissipation material is cured; supporting legs of the heat dissipation structure are fixed on the carrier structure via a bonding layer; and the bonding layer is cured. Therefore, the heat dissipation structure can be effectively fixed to the heat dissipation material and the bonding layer by completing the arrangements of the heat dissipation material and the bonding layer in stages.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 21, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pin-Jing SU, Liang-Yi HUNG, Yu-Po WANG
  • Publication number: 20240088054
    Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 14, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shu-Ting LAI, Chiu-Lien LI, Che-Min SU, Chun-Huan HUNG, Mu-Hung HSIEH, Cheng-Han YAO, Fajanilan Darcyjo Directo, Cheng-Liang HSU
  • Publication number: 20240079301
    Abstract: An electronic package is provided, in which a mesh structure is disposed between a circuit structure and an electronic element to increase the shunt path of current. Therefore, when the electronic element is used as an electrode pad of a power contact, the current can be passed through a conductive sheet of the circuit structure via the mesh structure, such that the power loss can be reduced and the IR drop of the electronic element can meet the requirements.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 7, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan LIN, Chia-Chu LAI, Min-Han CHUANG
  • Patent number: 11923337
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 5, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240072019
    Abstract: An electronic package is provided, in which an electronic module and a plurality of conductive pillars are embedded in an encapsulation layer, and a circuit structure is formed on the encapsulation layer, where the electronic module includes a carrier structure having conductive vias and at least a first electronic element disposed on the carrier structure. The first electronic element has a plurality of conductors in a form of conductive through-silicon vias, and at least a second electronic element is disposed on the circuit structure. Therefore, the design of the electronic module can reduce the layout area occupied by the electronic element on a surface of a packaging zone of the circuit structure, such that other functional elements can be added to the electronic package according to requirements, and the electronic package can improve functional requirements of the end product.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 29, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chung-Yu Ke, Liang-Pin Chen
  • Patent number: 11913121
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 27, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Publication number: 20240055402
    Abstract: An electronic package is provided, in which a stacking component and a plurality of conductive pillars are embedded in a packaging layer, and a routing structure is formed on the packaging layer, where the stacking component is formed by stacking a first electronic module and a second electronic module on each other, and a plurality of first conductive vias and a plurality of second conductive vias are served as the electrical connection paths between the first electronic module and the second electronic module, such that the transmission distance of electrical signals between a first electronic element in the first electronic module and a second electronic element in the second electronic module can be reduced.
    Type: Application
    Filed: December 8, 2022
    Publication date: February 15, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Lung-Yuan WANG, Feng KAO, Chiu-Ling CHEN, Hung-Kai WANG
  • Publication number: 20240047374
    Abstract: An electronic package is provided with a plurality of electronic elements disposed on a carrier structure and a shielding structure located between two adjacent electronic elements, where the shielding structure is formed with at least one cavity and shielding members located on opposite sides of the cavity, such that the shielding members are arranged between the two electronic elements. Therefore, the electromagnetic signal will be reflected via the shielding members to prevent the two electronic elements from electromagnetically interfering with each other.
    Type: Application
    Filed: October 18, 2022
    Publication date: February 8, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Chih-Chiang He, Chun-Chong Chien, Wen-Jung Tsai
  • Publication number: 20240049382
    Abstract: A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.
    Type: Application
    Filed: November 2, 2022
    Publication date: February 8, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chin-Wei Hsu, Jui-Kun Wang, Shu-Yu Ko, Fang-Wei Chang, Hsiu-Fang Chien
  • Publication number: 20240047336
    Abstract: An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 8, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ching-Chih Lin, Wen-Hsin Wang, Chieh-Yi Hsieh, Shin-Yu Wang, Yi-Chien Huang, Hsiu-Fang Chien