Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.

Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.

Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.

Abstract: A method for aligning a substrate on a lithographic apparatus includes providing a substrate having a first plurality of grating marks optimized for a beam of a first given diffraction order and a second plurality of grating marks optimized for a beam of a second given diffraction order on a lithographic apparatus. A first signal is generated using a first beam reflected from the first grating marks, the first beam being a beam of the first given diffraction order. A second signal is generated using a second beam reflected from the second grating marks, the second beam being a beam of the second given diffraction order. The substrate is aligned with respect to the apparatus using the first and second signals.

Abstract: A chemical mechanical polishing apparatus includes a polishing pad. A pad conditioner includes a static conditioner head having a surface area configured to contact and condition the pad. The surface area has a first end proximate to an axis of rotation of the pad and a second end remote from the axis of rotation of the pad. The first end defines a first arc length, and the second end defines a second arc length, where the first arc length and the second arc length are substantially identical.

Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.

Abstract: The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate. The ion energy may be varied continuously or in a stepwise manner over the time period, and may also be varied in a cyclical manner.

Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.

Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.

Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.

Abstract: The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate. The ion energy may be varied continuously or in a stepwise manner over the time period, and may also be varied in a cyclical manner.

Abstract: The present invention relates to a method and a device for reducing or eliminating coating on a backside and an outer edge of a substrate which is supported on a substrate support during plasma substrate processing, the substrate support supporting a central portion of the backside of the substrate. The device comprises a deposition ring configured to circumscribe the substrate support to abut an outer edge of the substrate support with an inner edge of the deposition ring. The deposition ring has an inner shielding region configured to abut a peripheral portion of the backside of the substrate which extends beyond the outer edge of the substrate support. The deposition ring has an edge shielding region configured to circumscribe the outer edge of the substrate without abutting the outer edge of the substrate.

Abstract: Embodiments of the present invention are directed to apparatus and methods of supplying a diluted process gas into a diffusion furnace for forming an oxide layer on a substrate in the diffusion furnace. One or more inlet gases are supplied into a chamber, and are heated in the chamber to generate an oxidizing gas such as steam. A dilution gas is flowed through a dilution gas line which extends through the chamber to permit heating of the dilution gas by the heat in the chamber without mixing the dilution gas and the oxidizing gas in the chamber. The oxidizing gas and the heated dilution gas are mixed downstream of the chamber prior to entry into the diffusion furnace.

Abstract: Embodiments of the present invention are directed to apparatus and methods of supplying a diluted process gas into a diffusion furnace for forming an oxide layer on a substrate in the diffusion furnace. One or more inlet gases are supplied into a chamber, and are heated in the chamber to generate an oxidizing gas such as steam. A dilution gas is flowed through a dilution gas line which extends through the chamber to permit heating of the dilution gas by the heat in the chamber without mixing the dilution gas and the oxidizing gas in the chamber. The oxidizing gas and the heated dilution gas are mixed downstream of the chamber prior to entry into the diffusion furnace.