Patents Assigned to Siltronic AG
  • Patent number: 12275079
    Abstract: A method cuts slices from workpieces using a wire saw having a wire array, which is tensioned in a plane between two wire guide rollers supported between fixed and floating bearings and having a chamber and a shell. The workpiece is fed through the wire array along a feed direction perpendicular to a workpiece axis, while simultaneously changing the shells' lengths by adjusting a temperature of the chambers with a first cooling fluid in accordance with a first correction profile specifying a change in the shells' lengths based on the depth of cut. The floating bearings are simultaneously axially moved by adjusting a temperature of the fixed bearings with a second cooling fluid in accordance with a second correction profile, which specifies a travel of the floating bearings based on the depth of cut. The first correction profile and the second correction profile are opposed to a shape deviation.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: April 15, 2025
    Assignee: SILTRONIC AG
    Inventors: Peter Wiesner, Wolfgang Gmach, Robert Kreuzeder
  • Patent number: 12251767
    Abstract: Slices are cut from workpieces using a wire saw having a wire array tensioned in a plane between two wire guide rollers each supported between fixed and floating bearings and comprising a chamber and a shell enclosing a core and having guide grooves for wires. During a cut-off operation, a workpiece is fed through the wire array perpendicular to a workpiece axis and the wire array plane. The workpiece is fed through the wire array while simultaneously: changing shell lengths by adjusting chamber temperatures in dependence on a depth of cut and a first correction profile; and moving the workpiece along the workpiece axis in accordance with a second correction profile. The correction profiles are opposed to a shape deviation.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: March 18, 2025
    Assignee: SILTRONIC AG
    Inventors: Peter Wiesner, Wolfgang Gmach, Robert Kreuzeder
  • Patent number: 12227870
    Abstract: A fused quartz crucible for pulling a single crystal of silicon by the Czochralski technique, has an inner side with an inner layer of fused quartz that forms a surface, the inner layer being provided with a crystallization promoter which on heating of the fused quartz crucible during use, in crystal pulling, causes crystallization of fused quartz to form b-cristobalite, wherein the concentration C of synthetically obtained SiO2 at a distance d from the surface is greater than the concentration of synthetically obtained SiO2 at a distance d2 from the surface, where d2 is greater than d. Multiple crystals can be grown while maintaining high crystal quality.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 18, 2025
    Assignee: SILTRONIC AG
    Inventors: Toni Lehmann, Dirk Zemke
  • Patent number: 12116694
    Abstract: An apparatus is configured to pull a single crystal of semiconductor material from a melt contained in a crucible. The apparatus includes: a rotatable pulling shaft; a rotatable crucible shaft; a double worm gear between a drive and the pulling shaft; and a further double worm gear between a further drive and the crucible shaft.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 15, 2024
    Assignee: SILTRONIC AG
    Inventors: Rolf Schmid, Helmut Bergmann, Werner Joedecke
  • Patent number: 12104274
    Abstract: Single crystal silicon cylindrical portions grown by the CZ method and highly doped with one or more n-type dopants so as to have a resistivity of not more than 2 m?cm are prepared by directing dopant in a gas flow from an external sublimation apparatus into the pulling chamber through or below the heat shield, to the bottom of an annular ring of the heat shield and from there through a plurality of nozzles toward the surface of the melt.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: October 1, 2024
    Assignee: SILTRONIC AG
    Inventors: Wolfgang Staudacher, Georg Raming
  • Patent number: 12083705
    Abstract: Semiconductor wafers are produced from a workpiece by means of a wire saw, by feeding the workpiece through an arrangement of wires tensioned between wire guide rollers and divided into wire groups, the wires moving in a running direction producing kerfs as wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups determined, and for each of the wire groups compensating movements of the wires of the wire group are induced as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 10, 2024
    Assignee: SILTRONIC AG
    Inventors: Axel Beyer, Stefan Welsch
  • Publication number: 20240246260
    Abstract: Semiconductor wafers having a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm, are produced from a workpiece by feeding the workpiece through a wire web tensioned between wire guide rollers and divided into wire groups, the wires producing kerfs as the wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups is used to compensate movements of the wires of the wire group as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.
    Type: Application
    Filed: April 5, 2024
    Publication date: July 25, 2024
    Applicant: SILTRONIC AG
    Inventors: Axel BEYER, Stefan WELSCH
  • Patent number: 11982015
    Abstract: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 14, 2024
    Assignee: SILTRONIC AG
    Inventors: Joerg Haberecht, Stephan Heinrich, Reinhard Schauer, Rene Stein
  • Patent number: 11972986
    Abstract: Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 30, 2024
    Assignee: Siltronic AG
    Inventors: Michael Boy, Christina Kruegler
  • Patent number: 11905617
    Abstract: A method produces semiconductor wafers of monocrystalline silicon. The method includes: pulling a cylindrical section of a single silicon crystal from a melt contained in a crucible, wherein the oxygen concentration in the cylindrical section is not more than 5×1017 atoms/cm3; subjecting the melt to a horizontal magnetic field; rotating the crucible at a rotational velocity and in a rotational direction during the pulling of the cylindrical section of the single crystal; and removing the semiconductor wafers of monocrystalline silicon from the cylindrical section of the single crystal. An amount of rotational velocity, averaged over time, is less than 1 rpm and the rotational direction is changed continually and the amplitude of the rotational velocity before and after the change in the rotational direction is not less than 0.5 rpm and not more than 3.0 rpm.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: February 20, 2024
    Assignee: SILTRONIC AG
    Inventors: Walter Heuwieser, Karl Mangelberger, Juergen Vetterhoeffer
  • Patent number: 11878359
    Abstract: A multiplicity of wafers are simultaneously cut from an ingot using a structured sawing wire having indentations and protrusions along its length, wherein the structured sawing wire is guided through grooves of two wire guide rolls, and a bottom of each groove, on which the structured wire bears, has a curved groove bottom with a radius of curvature which, for each groove, is equal to or up to 1.5 times as large as the radius of the envelope of the structured wire which the structured wire has in the respective groove.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 23, 2024
    Assignee: Siltronic AG
    Inventor: Georg Pietsch
  • Patent number: 11869942
    Abstract: A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness; an AlN nucleation layer; a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0<z; a first strain preserving block comprising ?5 and ?50 units of a first sequence of layers, the first sequence comprising an AlN layer and at least two AlGaN layers, and having a second average Al content y, wherein y a second strain building layer which is an AlxGal-xN layer having a third average Al content x, wherein 0?x<y; a second strain preserving block comprising ?5 and ?50 units of a second sequence of layers, the sequence comprising an AlN layer and at least one AlGaN layer, and having a fourth average Al content w, wherein x<w<y, and a GaN layer, wherein the layers between the AlN nucleation layer and the GaN layer form an AlGaN buffer.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: January 9, 2024
    Assignee: SILTRONIC AG
    Inventors: Sarad Bahadur Thapa, Martin Vorderwestner
  • Publication number: 20230417644
    Abstract: Unknown particles on a surface of a semiconductor wafer are classified by applying a range of particles of known chemical composition and different sizes onto a test wafer, measuring the sizes of a plurality of the particles and spectrally analyzing a makeup of the particles by energy-dispersive x-ray spectroscopy, followed by ascertaining a substantive content therefrom; creating a best-fit curve to the size and substantive content of the particles; measuring the particle size of an unknown particle and recording its spectrum by energy-dispersive x-ray spectroscopy and classifying the unknown particle as the result of a comparison of the size and the substantive content of the unknown particle with the best-fit curve.
    Type: Application
    Filed: October 26, 2021
    Publication date: December 28, 2023
    Applicant: Siltronic AG
    Inventors: Sebastian ANDRES, Robert HINTERLEUTHNER, Rudolf RUPP
  • Publication number: 20230332323
    Abstract: Single crystal silicon cylindrical portions grown by the CZ method and highly doped with one or more n-type dopants so as to have a resistivity of not more than 2 m?cm are prepared by directing dopant in a gas flow from an external sublimation apparatus into the pulling chamber through or below the heat shield, to the bottom of an annular ring of the heat shield and from there through a plurality of nozzles toward the surface of the melt.
    Type: Application
    Filed: December 3, 2020
    Publication date: October 19, 2023
    Applicant: SILTRONIC AG
    Inventors: Wolfgang STAUDACHER, Georg RAMING
  • Patent number: 11788201
    Abstract: Single crystals of semiconductor material are produced by an FZ method, wherein a molten zone is created between a feed rod and a growing single crystal; the method involving melting feed rod material in a high frequency magnetic field of a first induction coil; crystallizing material of the molten zone on top of the growing single crystal; rotating the growing single crystal about an axis of rotation and changing the direction of rotation and the speed of rotation according to a predetermined pattern; and imposing an alternating magnetic field of a second induction coil on the molten zone, wherein the alternating magnetic field is not axisymmetric with respect to the axis of rotation of the growing single crystal.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 17, 2023
    Assignee: Siltronic AG
    Inventors: Ludwig Altmannshofer, Goetz Meisterernst, Gundars Ratnieks, Simon Zitzelsberger
  • Publication number: 20230311363
    Abstract: A multiplicity of slices are simultaneously sliced from a workpiece during a slicing operation using a wire saw. A non-linear pitch function dTAR(WP) is selected dependent on a target thickness value function TTAR(WP), a pitch function dINI(WP) and a thickness value function TINI(WP), dTAR(WP) and adjacent grooves in the wire guide rollers are assigned a pitch at a position WP during the slicing operation, TINI(WP) slices which are obtained during a plurality of preceding slicing operations by means of the wire saw at the position WP are assigned a thickness value, dINI(WP), adjacent grooves in the wire guide rollers at the position WP are assigned a pitch during the preceding slicing operations, TTAR(WP) slices which are sliced off during the slicing operation at the position WP are assigned a target thickness value, WP denoting the axial position of the adjacent grooves with respect to the axes of the wire guide rollers.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 5, 2023
    Applicant: SILTRONIC AG
    Inventor: Georg PIETSCH
  • Publication number: 20230287566
    Abstract: Contamination of semiconductor wafers during coating and other operations is mitigated by passing the wafer through a tunnel with a slit providing a gas curtain which impinges upon the wafer as the wafer is transported from one station to the next station in the processing apparatus.
    Type: Application
    Filed: June 18, 2021
    Publication date: September 14, 2023
    Applicant: SILTRONIC AG
    Inventors: Patrick MOOS, Marco FELDMANN
  • Publication number: 20230287569
    Abstract: An apparatus for depositing a layer of semiconductor material on a substrate wafer. The apparatus includes a base ring between an upper and a lower dome, a susceptor as carrier of the substrate wafer during the deposition of the layer, a gas inlet and a gas outlet, an outgoing gas line and gas supply lines for passing process gas over an upper side face of the substrate wafer, a slit valve tunnel and a slit valve door, and a lifting and rotating unit for lifting and turning the susceptor and the substrate wafer. The apparatus also including an amorphous layer including silicon and hydrogen disposed over one or more stainless steel components of the apparatus.
    Type: Application
    Filed: July 16, 2021
    Publication date: September 14, 2023
    Applicant: SILTRONIC AG
    Inventor: Hannes HECHT
  • Publication number: 20230278111
    Abstract: A vacuum gripper for semiconductor workpieces is produced from at least one base material by means of an additive manufacturing method such as 3D printing. The method may also include printing various other feature of the vacuum gripper such as reinforcing structures and or seals. The gripper may include a plurality of suction openings and corresponding channels for providing a negative pressure when cooperating with a vacuum.
    Type: Application
    Filed: July 21, 2021
    Publication date: September 7, 2023
    Applicant: SILTRONIC AG
    Inventors: Sebastian GEISSLER, Ludwig LAMPRECHT
  • Publication number: 20230265581
    Abstract: An epitaxial layer is deposited on a substrate wafer by a method including measuring an edge geometry of the wafer, placing the wafer at a position in a pocket of a susceptor of a device for depositing the layer based on the edge geometry, heating the wafer, and passing a process gas over the wafer. Thickness characteristic values are assigned to edge portions based on the edge geometry. The position in the pocket is determined as function of an expected change in the thickness characteristic value to an eccentricity E, which is determined by prior testing of the device. The function is a result of the shape of the pocket which has a boundary having a circular circumference. The distance from the wafer to the boundary of the pocket is less at thicker edge portions and greater at thinner edge portion so the layer has thicknesses inverse to the wafer thicknesses.
    Type: Application
    Filed: July 21, 2021
    Publication date: August 24, 2023
    Applicant: SILTRONIC AG
    Inventors: Thomas STETTNER, Martin WENGBAUER