Abstract: The surface layer of a semiconductor wafer lying on a rotatable plate within an etching chamber is etched by a process whereby homogeneous etching of the surface is obtained by introducing an etching gas into the etching chamber in such a way that the flow of the etching gas is not directed directly to the wafer but is allowed first to distribute within the etching chamber before coming into contact with the surface of the semiconductor wafer to be etched.

Abstract: A semiconductor wafer comprising single-crystal silicon has defined concentrations of oxygen, nitrogen and hydrogen; the semiconductor wafer further contains BMD seeds having a density averaged over the radius of not less than 1×105 cm?3 and not more than 1×107 cm?3; surface defects having a density averaged over the radius of not less than 1100 cm?2; and BMDs, whose density is not lower than a lower limit of 5×108/cm3. The semiconductor wafers are produced by a process which enables obtention of the required ranges of concentrations of oxygen, nitrogen, hydrogen, BMD seeds, and BMD's.

Abstract: Single crystal semiconductor wafers comprise oxygen and an n-type dopant, and are produced by a process comprising providing a silicon melt containing n-type dopant in a quartz crucible, the melt having an initial height hM; heating the melt from the side by selectively supplying heat to an upper volume of the melt having an initial height hm, wherein hm is smaller than hM; pulling a single crystal of silicon from the melt by the CZ method with a pulling velocity V; heating the melt from above in the region of a phase boundary between the growing single crystal and the melt; heating the melt from above in the region of a surface of the melt; subjecting the melt to a magnetic field; counterdoping the melt with p-type dopant; and separating the semiconductor wafer of single-crystal silicon from the single crystal. An apparatus for accomplishing the process is also disclosed.

Abstract: A susceptor for holding a semiconductor wafer with an orientation notch during deposition of a layer on the wafer comprises a susceptor ring having a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area. The susceptor has four positions at which the structure differs from the structure at four further positions, the spacing from one of the four positions to the next of the four positions being 90°, the spacing from one of the four positions to the next further position being 45°, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other positions of the four positions of the susceptor.

Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.

Abstract: Single crystal silicon with <100> orientation is doped with n-type dopant and comprises a starting cone, a cylindrical portion and an end cone, a crystal angle being not less than 20° and not greater than 30° in a middle portion of the starting cone, the length of which is not less than 50% of a length of the starting cone, and edge facets extending from a periphery of the single crystal into the single crystal, the edge facets in the starting cone and in the cylindrical portion of the single crystal in each case having a length which is not more than 700 ?m.

Abstract: The diameter (dK) of a cylindrical section and of an end cone of a single crystal being pulled from a melt in a crucible, is determined by measuring the diameter (dK) of the single crystal at an interface with the melt while taking into account a lowering rate (vs) of a surface of the melt relative to the crucible, a lifting rate (vK) with which the crystal is raised relative to the crucible, and a conservation of mass, wherein a diameter of a cylindrical section of the single crystal, determined by means of observing a bright ring on the surface of the melt, and is used for a correction, a plausibility check or a comparison of the diameter (dK) of the single crystal.

Abstract: The invention relates to a silicon wafer having a radial variation of oxygen concentration of less than 7%, determined over the entire radius of the silicon wafer. The wafers are produced in the PV region with rotation of crystal and crucible in the same direction, and in the presence of a horizontal magnetic field of defined intensity.

Abstract: Semiconductor wafers useful for NAND circuitry and having a front side, a rear side, a middle and a periphery, have an Nv region which extends from the middle to the periphery; a denuded zone which extends from the front side to a depth of not less than 20 ?m into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 1×1013 vacancies/cm3; a concentration of oxygen of not less than 4.5×1017 atoms/cm3 and not more than 5.5×1017 atoms/cm3; a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which can be developed by means of a heat treatment into BMDs having a peak density of not less than 6.0×109/cm3, where the heat treatment comprises heating the semiconductor wafer to a temperature of 800° C. over a period of four hours and to a temperature of 1000° C. over a period of 16 hours. The wafers are produced by a unique RTA treatment of Nv wafers.

Abstract: A method of polishing a semiconductor wafer includes polishing a surface of the semiconductor wafer using a polishing pad while supplying a polishing agent slurry containing abrasives during a first step. The polishing pad is free of abrasives and includes a first surface that contacts the semiconductor wafer, the first surface having a surface structure including elevations. Supply of polishing agent slurry is subsequently ended and, in a second step, the surface of the semiconductor wafer is polished using the polishing pad while supplying a polishing agent solution having a pH value of at least 12 that is free of solids.

Abstract: A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness; an AlN nucleation layer; a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0<z; a first strain preserving block comprising ?5 and ?50 units of a first sequence of layers, the first sequence comprising an AlN layer and at least two AlGaN layers, and having a second average Al content y, wherein y a second strain building layer which is an AlxGal-xN layer having a third average Al content x, wherein 0?x<y; a second strain preserving block comprising ?5 and ?50 units of a second sequence of layers, the sequence comprising an AlN layer and at least one AlGaN layer, and having a fourth average Al content w, wherein x<w<y, and a GaN layer, wherein the layers between the AlN nucleation layer and the GaN layer form an AlGaN buffer.

Abstract: Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p+-doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer; an oxygen concentration of the substrate wafer of not less than 5.3×1017 atoms/cm3 and not more than 6.0×1017 atoms/cm3; a resistivity of the substrate wafer of not less than 5 m?cm and not more than 10 m?cm; and the potential of the substrate wafer to form BMDs as a result of a heat treatment of the epitaxially coated semiconductor wafer, where a high density of BMDs has a maximum close to the surface of the substrate wafer.

Abstract: A semiconductor wafer made of single-crystal silicon has an oxygen concentration (new ASTM) of not less than 4.9×1017 atoms/cm3 and not more than 6.5×107 atoms/cm3 and a nitrogen concentration (new ASTM) of not less than 8×1012 atoms/cm3 and not more than 5×1013 atoms/cm3, wherein a frontside of the semiconductor wafer is covered with an epitaxial layer made of silicon, wherein the semiconductor wafer comprises BMDs of octahedral shape whose mean size is 13 to 35 nm, and whose mean density is not less than 3×108 cm?3 and not more than 4×109 cm?3, as determined by IR tomography.

Abstract: The invention relates to a silicon wafer having a radial variation of oxygen concentration of less than 7%, determined over the entire radius of the silicon wafer. The wafers are produced in the PV region with rotation of crystal and crucible in the same direction, and in the presence of a horizontal magnetic field of defined intensity.

Abstract: A single crystal is pulled by an FZ method, in which a polycrystal is melted by means of an electromagnetic melting apparatus and then recrystallized, wherein a first phase (P1) a lower end of the polycrystal, which is moved toward the melting apparatus, is melted by the melting apparatus to form a drop, and in a second phase (P2) a monocrystal line seed is attached to the lower end of the polycrystal and is melted beginning from an upper end of the seed, where a power (P) of the melting apparatus during the first phase (P1) and during the second phase (P2) is predetermined at least temporarily in dependence on a temperature and/or geometrical dimensions of crystal material used which comprises the drop and/or the seed and/or the polycrystal.

Abstract: A single crystal is pulled by the FZ method, in which in a first phase, a lower end of the polycrystal is melted by the melting apparatus, in a second phase, a monocrystalline seed is attached to the lower end of the polycrystal, and in a third phase, between a lower section of the seed and the polycrystal, a thin neck section is formed whose diameter is smaller than that of the seed, where the power of the melting apparatus before the third phase is dynamically adapted in dependence on a position of a lower phase boundary (PU) between liquid material and solid material on the part of the seed, and where the power of the melting apparatus during the third phase is dynamically adapted in dependence on the position of an upper phase boundary (PO) between liquid material and solid material on the part of the polycrystal plant.

Abstract: Semiconductor wafers, are processed, using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

Abstract: Semiconductor wafers with an epitaxial layer are produced in a deposition chamber by placing a substrate wafer in the edge region of the rear side of the substrate wafer onto a placement area of a susceptor; loading the deposition chamber with the susceptor and the substrate wafer lying on the susceptor by contacting the susceptor and transporting the susceptor and the substrate wafer lying on the susceptor from a load lock chamber into the deposition chamber; depositing an epitaxial layer on the substrate wafer; and unloading the deposition chamber by contacting the susceptor and transporting the susceptor and a semiconductor wafer with epitaxial layer, the semiconductor wafer having been produced in the course of depositing the epitaxial layer and lying on the susceptor, from the deposition chamber into the load lock chamber.

Abstract: A separating apparatus for polysilicon has at least one screen plate, comprising a feed region for polysilicon, a profiled region having peaks and valleys, a region having screen apertures which adjoins the profiled region, and a takeoff region, wherein the screen apertures widen in the direction of the takeoff region, and a separating plate which is horizontally and vertically displaceable is arranged below the screen apertures.

Abstract: Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.