Abstract: A computing host includes a host processor and a communication processor both coupled in communication with a network and a storage device. The host processor receives a file request for transferring a file between the network the storage device, determines that the file request is to be performed by using a direct file transfer, generates a command based on the file request, and provides the command to the communication processor. The communication processor transfers the file between the network and the storage device based on the command without passing the file through the host processor. Additionally, the communication processor can transmit the file to the network.

Abstract: A computing host transfers a file between a computer network and a storage device without passing the file through a host processor of the computing host. A communication processor of the computing host receives a file request from the computer network and either processes the file request to directly transfer the file between the computer network and the storage device or passes the file request to the host processor for processing. Additionally, the communication processor writes the file into a cache memory and processes a subsequent file request on the file in the cache memory.

Abstract: A computing host includes a communication processor that receives a file request from a computer network for transferring a file between the computer network and a storage device. If the file is directly transferable between the computer network and the storage device without a need for processing the file by a host processor of the computing host, the communication processor performs the file transfer. Otherwise, the host processor processes the file and performs the file transfer.

Abstract: A computing host includes a communication processor that receives a command for transferring a file between a storage device and a network. The command includes one or more identifiers for identifying one or more data payloads in the file. The communication processor also receives a header for each data payload. The communication processor reads the file in the storage device based on the command. Additionally, the communication processor generates a data packet for each data payload in the file, which includes the data payload and the header for the data payload. The communication processor transmits each data packet to the computer network without passing the data packet through a host processor of the computing host.

Abstract: A secure storage device includes a storage medium configured to securely store data received from a host. The storage device further includes a host interface configured to transfer data between the host and the storage device and an encryption engine. The encryption engine is configured to encrypt data received from a host using a key and provide the encrypted data to the storage medium for storage. The encryption engine is further configured to decrypt encrypted data received from the storage medium and provide the data to the host via the host interface. In response to a predetermined condition, the storage device is configured to disable the encryption engine thereby preventing the encrypted data stored thereon from being decrypted.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.

Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other.

Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. The purge of the flash storage device is subsequently verified.

Abstract: A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page.

Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command while allowing the flash storage device to be used subsequent to the purge. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. Subsequent to the purge, certain control data is reconstructed to allow subsequent use of the flash storage device.

Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command based on the authentication data, and executes the control command to allow the host device to access the secure memory.

Abstract: A registered dual in-line memory module is configured with multiple random access memory chips and a DRAM register configured to receive address and control signals from a memory controller. The DRAM register distributes the address and control signals to the random access memory chips, thereby providing the memory controller access to the chips. The module further includes a control register configured to store control bits for setting operating modes of the registered dual in-line memory module. The control bits are software programmable using signals received from the memory controller.

Abstract: A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.

Abstract: A data storage system using flash storage maintains a status indicator corresponding to data written into the flash storage. The status indictor of the data indicates whether a disruption, such as a power disruption or a device disconnection, occurred when the data was being written into the flash storage. The data storage system determines whether the data may be corrupted based on one or more of the status indictors. The data storage system may make this determination at a selected time or after a power-up of the data storage system. If the data is determined to possibly be corrupted, the data storage system may optionally discard the corrupted data from the flash storage or flag the corrupted data for future removal.

Abstract: A memory and storage device includes a data management system for transferring data units referenced by logical addresses. The data management system maps the logical addresses to sequential virtual addresses according to the order the data units are received. The data management system also maps the sequential virtual addresses to sequential physical addresses in a memory block of a memory device. Additionally, the data management system can modify a data unit in the memory block by copying any other valid data units in the memory block to another memory block and writing the modified data unit into this other memory block. The data management system writes the valid data units and the modified data unit into sequential physical addresses of this other memory block.

Abstract: A DDR2 SDRAM memory module having memory chips arranged bilaterally symmetrical on the module. A register chip is arranged on each of two faces of the memory module, with each register chip coupled to half of the memory chips.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.