Abstract: A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

Abstract: An image sensing device may include: a substrate including a back side and a front side; imaging pixels configured to receive incident light from the back side and each structured to produce photocharge in response to the received incident light at each imaging pixel; a plurality of taps located at a depth from the front side of the substrate and configured to generate a current within the substrate and capture photocharge generated by the imaging pixels and migrated by the current, wherein the plurality of taps is distributed in the imaging pixels such that two or more of the plurality of taps are located within each imaging pixel; and a capping region formed in each imaging pixel to surround the two or more taps included in each imaging pixel, wherein a lower portion of the capping region is spaced apart from the back side by a predetermined distance.

Abstract: Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

Abstract: Disclosed is a device for correcting an erasure including a defect symbol location generating unit and an erasure decoding unit. The defect symbol location generating unit generates third information on a location of an erasure. The erasure decoding unit performs an erasure correcting operation on a read codeword read from a memory unit based on the third information.

Abstract: A fail data augmentation device may input a plurality of fail data units to a data augmentation model, obtain a plurality of augmented fail data units outputted from the data augmentation model, and delete one or more of the augmented fail data units. The plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of a plurality of banks included in a random access memory, a second parameter indicating one of a plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of a plurality of hex units included in the matrix corresponding to the second parameter respectively.

Abstract: Electronic device and method to facilitate control frame transmission are provided. The electronic device comprises an interconnection controller including a physical layer circuit for signal transmission, a signaling interface, a link controller coupled to the physical layer circuit through the signaling interface, and a bypass path coupled to the link controller for control frame transmission. The link controller is configured to transmit data to the physical layer circuit through the signaling interface, and to transmit a control frame to the physical layer circuit through a signal path including the bypass path to bypass at least one circuit stage of the link controller.

Abstract: A semiconductor memory apparatus is configured to perform a mismatch compensation operation of a bitline sense amplifier and enable a wordline electrically coupled with a bitline, after electrically isolating an input node of the bitline sense amplifier and the bitline. When the mismatch compensation operation of the bitline sense amplifier is completed, the semiconductor memory apparatus is configured to electrically couple the bitline and the input node of the bitline sense amplifier to develop a voltage level difference between the bitline and a bitline bar.

Abstract: Provided herein is a memory device and a method of performing a verify operation of the memory device. The memory device includes a memory cell array including memory cells, a source line discharge transistor configured to couple a source line of the memory cell array to a ground, a voltage generator configured to generate a gate voltage that is applied to a gate of the source line discharge transistor, and a control logic configured to determine the gate voltage depending on changes in threshold voltages of the memory cells in response to a verify operation on the memory cells performed in each of a plurality of program loops and to control the voltage generator to generate the determined gate voltage.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.

Abstract: A semiconductor memory device includes: a gate electrode stack vertically stacked over a substrate with bent gate pads, the bent gate pads portion of the gate electrode stack having a step-shaped structure; an inter-layer dielectric layer covering the bent gate pads; and a plurality of contact plugs respectively coupled to the bent gate pads by penetrating the inter-layer dielectric layer, wherein the bent gate pads include angled corner portions of different sizes.

Abstract: A semiconductor device includes a gate structure including alternately stacked conductive layers and insulating layers, channel structures passing through the gate structure. Each of the conductive layers may include a first portion having a first thickness and a second portion having a second thickness thicker than the first thickness, and the second portion may include a first metal layer, a second metal layer in the first metal layer, and a first barrier layer interposed between the first metal layer and the second metal layer.

Abstract: A semiconductor device includes an error correction buffer circuit that generates an error correction signal when one of a first write operation and a second write operation is performed based on a command address, a first chip selection signal, a second chip selection signal, first data, and second data; a first data storage block that stores the first data when the first write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal, a second data storage block that stores the second data when the second write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal; and an error correction signal storage circuit that stores the error correction signal when one of the first write operation and the second write operation is performed based on the command address.

Abstract: Disclosed is an image sensor including first and second pixels arranged in a first row, for outputting first and second pixel signals through first and third column lines during a unit row time; third and fourth pixels arranged in a second row, for outputting third and fourth pixel signals through second and fourth column lines during the unit row time; an alignment circuit for aligning the first to fourth pixel signals for each row, and outputting first to fourth alignment signals, according to control signals; a first signal conversion circuit for generating a first depth information signal corresponding to a difference in voltage levels between the first and second alignment signals, through one A/D conversion operation; and a second signal conversion circuit for generating a second depth information signal, corresponding to a difference in voltage levels between the third and fourth alignment signals, through one A/D conversion operation.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.

Abstract: A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

Abstract: A storage device includes a plurality of memory devices, a plurality of cores controlling the plurality of memory devices, and a host interface configured to select a first core of the plurality of cores to store a plurality of meta data in a memory device controlled by the first core, and configured to switch to a second core from the plurality of cores to store the plurality of meta data in a memory device controlled by the second core, when the number of operations for storing a first meta data, from among the plurality of meta data, by the first core exceeds a threshold value.

Abstract: A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.

Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.

Abstract: A semiconductor device may include: a first conductive layer; a second conductive layer spaced apart from the first conductive layer; a tunnel insulating layer interposed between the first conductive layer and the second conductive layer and disposed adjacent to the first conductive layer; a charge blocking layer interposed between the first conductive layer and the second conductive layer and disposed adjacent to the second conductive layer; and a selector layer interposed between the tunnel insulating layer and the charge blocking layer, wherein the semiconductor device functions as a self-selecting memory.

Abstract: A signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.