Abstract: Disclosed is a continuous time linear equalizer circuit having a higher bandwidth by a plurality of filters connected to different signal paths in a T-coil circuit.

Abstract: A memory system may include: a nonvolatile memory device; a volatile memory device to which power is suspended in the sleep mode; and a controller configured to temporarily store internal data in the volatile memory device, the internal data being generated during processing of an operation of the nonvolatile memory device. When a sleep command is received by the memory system from a host, the controller may output the internal data stored in the volatile memory device to the host in response to the sleep command, and then may transfer an acknowledgement for an entry into the sleep mode to the host and enter the sleep mode.

Abstract: A counting device includes a control unit suitable for generating a control signal including a first control signal and a second control signal, a first operation unit suitable for performing a logic operation for pixel signals of a pixel array and a control signal, wherein pixel signals of used column in the pixel array are transferred by using the first control signal, and pixel signals of unused column in the pixel array are blocked by using the second control signal during a binning mode operation, a second operation unit suitable for performing a logic operation for a counter clock and an output signal of the first operation unit, and a counting unit suitable for counting an output signal of the second operation unit.

Abstract: A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.

Abstract: A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for a merge operation based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block for the merge operation, and wherein the controller converts the victim block into a free memory block during the merge operation and reuses the free memory block to store data.