Abstract: An image sensing device includes an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic region configured to generate an image based on the electrical signals from the unit pixels, light reception elements disposed over the upper substrate and configured to transmit the incident light to the pixel region, an insulation layer disposed between the upper substrate and the lower substrate, a light reception alignment mark disposed in the first peripheral region and configured to assist positioning of the light reception elements, and an alignment pattern disposed between the first peripheral region and the second peripheral region and in the insulation layer. The alignment pattern is configured to absorb light used to measure the light reception alignment mark.
Type:
Grant
Filed:
April 12, 2021
Date of Patent:
July 15, 2025
Assignee:
SK HYNIX INC.
Inventors:
Seok Jae Shin, Woo Yung Jung, Jae Hyun Park
Abstract: An image sensing device includes a plurality of pixel groups, each pixel group including first to fourth unit pixels that are configured to respond to incident light and generate electrical signals, and wherein each of the first to fourth unit pixels of a pixel group includes optical filters operable to transmit incident light corresponding to a same color, wherein the first unit pixel and the second unit pixel that are included in the pixel group are located adjacent to each other and include portions of a first microlens, and wherein a light reception area of the third unit pixel of the pixel group has a size smaller than a size of a light reception area of the fourth unit pixel of the pixel group.
Abstract: An apparatus comprises a controller comprising an interface comprising circuitry to communicate with a host computing device; and a relocation manager comprising circuitry, the relocation manager to provide, for the host computing device, an identification of a plurality of data blocks to be relocated within a non-volatile memory; and relocate at least a subset of the plurality of data blocks in accordance with a directive provided by the host computing device in response to the identification of the plurality of data blocks to be relocated.
Abstract: A method and controller for operating a memory system in communication with a host. The method and controller logically arrange a sequence of reclaim sub-groups within a memory device. The method and controller process the reclaim sub-groups according to the sequence to control the memory device to perform garbage collection on the reclaim sub-groups in the memory device. In the sequence, the reclaim sub-groups are processed during the garbage collection such that at least one re-ordered data sequence in the sequence of the reclaim sub-groups being processed has re-ordered valid data that is not clumped.
Type:
Grant
Filed:
March 2, 2023
Date of Patent:
July 15, 2025
Assignee:
SK hynix NAND Product Solutions Corp.
Inventors:
David J. Pelster, Mark Golez, Daniel R. McLeran, Nathan Koch, Paul Ruby
Abstract: A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.
Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory device controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.
Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, and an oxide layer provided adjacent to the first magnetic layer, the first magnetic layer being provided between the non-magnetic layer and the oxide layer, and the oxide layer containing a rare earth element, boron (B), and oxygen (O).
Type:
Grant
Filed:
September 10, 2021
Date of Patent:
July 8, 2025
Assignees:
Kioxia Corporation, SK hynix Inc.
Inventors:
Tadaaki Oikawa, Youngmin Eeh, Eiji Kitagawa, Kazuya Sawada, Taiga Isoda, Ku Youl Jung, Jin Won Jung
Abstract: A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.
Abstract: Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.
Type:
Grant
Filed:
October 3, 2022
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Min Kyu Kim, Jong Hyun Ra, Jin Ho Seo, Kyoung Mook Lim, Hoe Sam Jeong
Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.
Type:
Grant
Filed:
May 26, 2022
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Won Geun Choi, Jang Won Kim, Jung Shik Jang
Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
Type:
Grant
Filed:
February 15, 2022
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee
Abstract: According to an embodiment of the present technology, a storage device may include a memory device including a secure storage area for storing therein data to be accessed according to authentication; an access mode memory configured to store therein information of device access mode regarding an operation mode for the secure storage area; and a memory controller configured to receive a command regarding the secure storage area from an external host and process the command according to whether information of host access mode included in the command matches the information of the device access mode.
Type:
Grant
Filed:
September 12, 2022
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Hui Won Lee, Byung Jun Kim, Taek Gyu Lee, Young Kyu Jeon
Abstract: A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.
Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.
Abstract: A semiconductor device includes a control circuit configured to generate a buffer enable signal that is enabled when patterns of a strobe signal and an inverted strobe signal are preset patterns after the start of a write operation and configured to generate an internal strobe signal by dividing frequencies of an input strobe signal and an inverted input strobe signal, and a buffer circuit configured to generate the input strobe signal and the inverted input strobe signal from the strobe signal and the inverted strobe signal that are received when the buffer enable signal is enabled and configured to generate transfer data by receiving data for performing the write operation when the buffer enable signal is enabled.
Abstract: A method for operating a system including a host and at least one solid state drive (SSD). The method identifies a workload associated with the SSD, recognizes a power state of the SSD, and controls allocation and/or deallocation of hardware resources for the identified workload per a budgeted target for the power state.
Type:
Grant
Filed:
September 8, 2022
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Seong Won Shin, Kailash Mallikarjunaswamy
Abstract: A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.
Type:
Grant
Filed:
July 21, 2021
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Jun Ku Ahn, Gwang Sun Jung, Jong Ho Lee, Uk Hwang
Abstract: A storage device of the present disclosure includes a memory device including a system memory storing system information used in an operation, and a register storing a register value indicating that the system information is a first state or a second state, and a memory controller configured to control the memory device to receive the register value from the memory device when power is turned on, and to initialize the system information stored in the system memory when the received register value indicates that the system information is the first state.
Abstract: A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.
Type:
Grant
Filed:
September 1, 2023
Date of Patent:
July 8, 2025
Assignee:
SK hynix Inc.
Inventors:
Ji Hwan Park, Kyung Hoon Kim, Se Ra Jeong, Ha Jun Jeong, Jae Hoon Cha
Abstract: Methods, systems, and devices for alleviating a bandwidth bottleneck during an embedding operation are described. An example storage device, based on the disclosed technology, includes a memory device configured to store matrix data, a memory controller, coupled to the memory device, configured to receive, from a host, non-zero data and the index of the non-zero data, and generate vector data based on the non-zero data and the index, and an operating component, coupled to the memory device and the memory controller, configured to perform a multiplication operation between the matrix data and the vector data.