Patents Assigned to SKYECHIP SDN BHD
  • Publication number: 20250253771
    Abstract: The present invention relates to a circuitry system (200) for regulating power supply, characterized by: a feedforward amplifier (100) comprising a clock generator (10) and a load circuit (20) for producing current during functional requirements; wherein the clock generator (10) comprises a toggle detector circuit (12) for generating feedforward enable signal when toggling input clock signal is detected; wherein the load circuit (20) comprises a feedforward pass gate for receiving feedforward enable signal, a load circuitry (24), a variable bias voltage controller and a level shifter (22) for controlling the feedforward pass gate.
    Type: Application
    Filed: August 26, 2024
    Publication date: August 7, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Jaw Wen CHEW, Tze Jian CHOW, How Hwan WONG, Chun Wei LEE
  • Patent number: 12380056
    Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: August 5, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yu Ying Ong, Chee Hak Teh
  • Publication number: 20250247323
    Abstract: The present invention relates to a computer-implemented method of generating a Network-on-Chip routing table, said method comprising the steps of: identifying source and destination by coordinates; sorting source-destination list based on user-input constraints; iterating source-destination pairs in the sorted source-destination list to find a shortest routing path from the source to the destination; splitting each source-destination pair to multiple sub source-destination pairs based on one of the user-input constraints; iterating each of the sub source-destination pairs to find a shortest routing path in a sub source-destination list; creating routing table for each sub source-destination pair based on the user-input constraints; combining the routing tables of sub source-destination pairs to generate a source-destination pairs routing table; performing routing table deadlock detection before proceeding to generate a routing table for next source-destination pair; wherein the user-input constraints comprisi
    Type: Application
    Filed: July 29, 2024
    Publication date: July 31, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Siew Chin LIM, Yin Chong HEW, Chee Hak TEH
  • Publication number: 20250240022
    Abstract: The invention relates to a digital delay line of a memory system is characterized by: a coarse delay line receiving a high-speed input clock; and a fine delay line transmitting an interface output clock to transceivers; wherein the coarse delay line is configured to perform clock division from a frequency of the high-speed input clock to a frequency of the interface output clock and to delay divided output clock; wherein the coarse delay line comprising a dual-edge triggered flip-flop to produce a shifted divided clock and a clock mux to bypass the high-speed input clock when delay shifting is not needed; wherein the fine delay line is configured to provide a finer delay step size. Further, a method of adjusting the timing of clocks within a memory system using a digital delay line of a memory system is also disclosed.
    Type: Application
    Filed: September 17, 2024
    Publication date: July 24, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Hoong Chin NG, How Hwan WONG
  • Publication number: 20250182811
    Abstract: The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.
    Type: Application
    Filed: January 26, 2024
    Publication date: June 5, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Tze Jian CHOW, Hoong Chin NG, Tat Hin TAN, Chee Hak TEH
  • Publication number: 20250141779
    Abstract: The invention relates to a computer-implemented method (100) of generating and assigning identifier information to each router in a network-on-chip for arbitrating data packets. The method (100) comprises the steps of: generating and assigning a planar-axis coordinate, Z, for each router; generating and assigning an ascending value to each router link layer for every link between two routers of the same coordinate; selecting the origin router with the smallest value; assigning a coordinate comprising a horizontal-axis (X) and a vertical-axis (Y); calculating the distance of the coordinates; generating and assigning coordinates to adjacent routers; applying coordinate shrinking to get all coordinates in positive integer numbers with optimized ascending order; and repeating the steps to complete the generation and assignment of coordinates to all planar-axis routers.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 1, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: YIN CHONG HEW, SOON HOCK SAW, KEE XIAN LOW, YEONG TAT LIEW
  • Publication number: 20250138623
    Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, MUHAMAD AIDIL BIN JAZMI, Yeong Tat LIEW, Weng Li LEOW
  • Patent number: 12210633
    Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 28, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yu Ying Ong, Muhamad Aidil Bin Jazmi, Soon Chieh Lim, Chee Hak Teh
  • Patent number: 12199884
    Abstract: A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 14, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yeong Tat Liew, Yu Ying Ong, Soon Chieh Lim, Weng Li Leow, Chee Hak Teh
  • Patent number: 12149407
    Abstract: The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (101), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element (103) and a plurality of basic network elements (105); whereby said secondary network (101) is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: November 19, 2024
    Assignee: SKYECHIP SDN BHD
    Inventors: Soon Chieh Lim, Chuen Heong Khuan, Chee Hak Teh
  • Patent number: 12125518
    Abstract: The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: October 22, 2024
    Assignee: SkyeChip Sdn Bhd
    Inventors: Soon Chieh Lim, Hoong Chin Ng, Ching Liang Ooi, Chee Hak Teh
  • Publication number: 20240297846
    Abstract: The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 5, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, Weng Li LEOW, Yeong Tat LIEW, Chuen Heong KHUAN, Manobindra GANDHI, Muhamad Aidil Bin JAZMI
  • Publication number: 20240192721
    Abstract: The present invention relates to a system (100 or 200) for aligning a programmable clock or strobe. The system (100 or 200) comprises a first programmable delay unit (1a) for receiving the programmable clock or strobe, characterized by a second programmable delay unit (1b) connected in parallel to the first programmable delay unit (1a) for receiving the programmable clock or strobe, a switch (2) for switching one of the two programmable delay units (1a or 1b) to service the programmable clock or strobe so as to allow the other programmable delay unit (1a or 1b) to adjust the other programmable clock or strobe, and a control logic component (3) for handling the switching of the switch (2), in which the switch (2) swaps in the adjusted programmable clock or strobe to service a downstream clocktree or strobe path after the programmable clock or strobe is adjusted. The present invention also relates to a method for aligning a programmable clock or strobe.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 13, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: TAT HIN TAN, SOON CHIEH LIM, ZHEN PENG CHOK, CHEE HAK TEH, CHEAU NIH TAN
  • Publication number: 20240163223
    Abstract: The present invention relates to a method (100) for network-on-chip arbitration. The method (100) comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: YEONG TAT LIEW, YU YING ONG, SOON CHIEH LIM, WENG LI LEOW, CHEE HAK TEH
  • Patent number: 11829643
    Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 28, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong, Weng Li Leow, Muhamad Aidil Bin Jazmi
  • Publication number: 20230129791
    Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 27, 2023
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Weng Li LEOW, Muhamad Aidil Bin JAZMI
  • Patent number: 11609709
    Abstract: A memory controller system comprising a scheduling module, a data buffer module, a global order buffer module and a linked-list controlling module. The linked-list controlling module is configured to receive and process a first command comprising a write command or a read command. The linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module. If the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 21, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong
  • Patent number: 11575383
    Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: February 7, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong, Wong Ging Yeon Mark, Tat Hin Tan, Soong Khim Chew
  • Patent number: 11509312
    Abstract: An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: November 22, 2022
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Soon Chieh Lim, Ging Yeon Mark Wong, How Hwan Wong
  • Patent number: 11442878
    Abstract: A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: September 13, 2022
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Soon Chieh Lim