Abstract: The present invention relates to a network-on-chip architecture (100), characterized by: a plurality of stampable partition (200), each partition including one or more router (10) adapted for communication, registers and pre-built communication links established in cardinal directions or other directions, and one or more configuration bus node (20) deposited in each partition (200) connecting to the registers (40); a system integrator connecting a system operator (60) to one of the configuration bus node (20); wherein the system operator (60) initializes a path mapping between the configuration bus node (20) forming a secondary configuration network and access the registers (40) in each partition to program the registers (40) with routing data A method of processing data at the network-on-chip architecture (100) is also disclosed herein.

Abstract: A feedforward circuitry system for regulating voltage includes a voltage regulator for generating a regulated voltage, a bias generator operatively connected to the voltage regulator for generating a sub-threshold gate bias, a plurality of coupling capacitors, at least one of the coupling capacitors operatively connected to the bias generator for reading the sub-threshold gate bias and a feedforward amplifier operatively coupled with at least one of the coupling capacitors, characterized in that the plurality of coupling capacitors being configured to direct AC-couple an output transition of CMOS logic gates. A method for regulating voltage in a feedforward circuitry system through a direct AC-coupling is also provided.

Abstract: The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

Abstract: The present invention relates to a computer-implemented design synchronizing system (1) for designing floorplan of electronic systems.

Abstract: The present invention relates to a circuitry system (1). The circuitry system (1) comprises a reservoir power rail (12), a regulated power rail (14), a logic circuitry (18) connected to the regulated power rail (14), wherein each of the reservoir power rail (12), regulated power rail (14) and logic circuitry (18) is connected to respective voltage supply source (16), characterized by a dynamic decoupling capacitor (10) connecting the reservoir power rail (12) to the regulated power rail (14), and in communication with the logic circuitry (18), wherein the dynamic decoupling capacitor (10) is configured to match a total-charge of injected-current, ldecap, from the reservoir power rail (12) with a total-charge of load-current, lload, supplying to the logic circuitry (18). A method for regulating voltage of the circuitry system (1) is also disclosed herein.

Abstract: A process for regulating power supply using a low-dropout regulator may include detecting voltage levels based on a predetermined first voltage level as high voltage and a second voltage level as medium voltage, wherein the high voltage is powered up followed by the medium voltage; a shifting bias mechanism when high voltage is detected during the initial power up of the high voltage rail, including turning on the overvoltage protection circuit, lowering actual bias voltage to counter back the required high bias voltage, and applying the actual bias voltage for a feedback system; performing the fix bias mechanism when medium voltage is detected, including turning off the overvoltage protection circuit and applying a fixed voltage reference to an actual pass gate of source follower for the feedback system enabling an instant startup together with the medium voltage when it powers up.

Abstract: The present invention relates to a system (100 or 200) for aligning a programmable clock or strobe. The system (100 or 200) comprises a first programmable delay unit (1a) for receiving the programmable clock or strobe, characterized by a second programmable delay unit (1b) connected in parallel to the first programmable delay unit (1a) for receiving the programmable clock or strobe, a switch (2) for switching one of the two programmable delay units (1a or 1b) to service the programmable clock or strobe so as to allow the other programmable delay unit (1a or 1b) to adjust the other programmable clock or strobe, and a control logic component (3) for handling the switching of the switch (2), in which the switch (2) swaps in the adjusted programmable clock or strobe to service a downstream clocktree or strobe path after the programmable clock or strobe is adjusted. The present invention also relates to a method for aligning a programmable clock or strobe.

Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.

Abstract: A coherent system including a plurality of processing units; an interconnect comprising a snoop filter, a conflict buffer to track in-progress or outstanding snoop, and a snoop state machine for managing snoop requests and snoop responses between the snoop filter, the conflict buffer and the processing units; wherein the snoop filter is configured to copy cacheline data of a cacheline that the processing unit reads on, match the cacheline address with tags of the snoop filter, and receive the snoop responses; wherein the conflict buffer is configured to indicate a hit or miss status based on the matching of the snoop filter and to send peer-cache snoop requests to different processing units. Further, a method of maintaining cache coherence using the coherent system also disclosed.

Abstract: The present invention relates to a circuitry system (200) for regulating power supply, characterized by: a feedforward amplifier (100) comprising a clock generator (10) and a load circuit (20) for producing current during functional requirements; wherein the clock generator (10) comprises a toggle detector circuit (12) for generating feedforward enable signal when toggling input clock signal is detected; wherein the load circuit (20) comprises a feedforward pass gate for receiving feedforward enable signal, a load circuitry (24), a variable bias voltage controller and a level shifter (22) for controlling the feedforward pass gate.

Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.

Abstract: The present invention relates to a computer-implemented method of generating a Network-on-Chip routing table, said method comprising the steps of: identifying source and destination by coordinates; sorting source-destination list based on user-input constraints; iterating source-destination pairs in the sorted source-destination list to find a shortest routing path from the source to the destination; splitting each source-destination pair to multiple sub source-destination pairs based on one of the user-input constraints; iterating each of the sub source-destination pairs to find a shortest routing path in a sub source-destination list; creating routing table for each sub source-destination pair based on the user-input constraints; combining the routing tables of sub source-destination pairs to generate a source-destination pairs routing table; performing routing table deadlock detection before proceeding to generate a routing table for next source-destination pair; wherein the user-input constraints comprisi

Abstract: The invention relates to a digital delay line of a memory system is characterized by: a coarse delay line receiving a high-speed input clock; and a fine delay line transmitting an interface output clock to transceivers; wherein the coarse delay line is configured to perform clock division from a frequency of the high-speed input clock to a frequency of the interface output clock and to delay divided output clock; wherein the coarse delay line comprising a dual-edge triggered flip-flop to produce a shifted divided clock and a clock mux to bypass the high-speed input clock when delay shifting is not needed; wherein the fine delay line is configured to provide a finer delay step size. Further, a method of adjusting the timing of clocks within a memory system using a digital delay line of a memory system is also disclosed.

Abstract: The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

Abstract: The invention relates to a computer-implemented method (100) of generating and assigning identifier information to each router in a network-on-chip for arbitrating data packets. The method (100) comprises the steps of: generating and assigning a planar-axis coordinate, Z, for each router; generating and assigning an ascending value to each router link layer for every link between two routers of the same coordinate; selecting the origin router with the smallest value; assigning a coordinate comprising a horizontal-axis (X) and a vertical-axis (Y); calculating the distance of the coordinates; generating and assigning coordinates to adjacent routers; applying coordinate shrinking to get all coordinates in positive integer numbers with optimized ascending order; and repeating the steps to complete the generation and assignment of coordinates to all planar-axis routers.

Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.

Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

Abstract: A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.

Abstract: The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (101), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element (103) and a plurality of basic network elements (105); whereby said secondary network (101) is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.

Abstract: The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.